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AD9510BCPZ-REEL7 Datasheet(PDF) 7 Page - Analog Devices

No. de pieza AD9510BCPZ-REEL7
Descripción Electrónicos  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9510BCPZ-REEL7 Datasheet(HTML) 7 Page - Analog Devices

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AD9510
Rev. A | Page 7 of 60
TIMING CHARACTERISTICS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL
Termination = 50 Ω to VS − 2 V
Output level 3Ch (3Dh) (3Eh) (3Fh)<3:2> = 10b
Output Rise Time, tRP
130
180
ps
20% to 80%, measured differentially
Output Fall Time, tFP
130
180
ps
80% to 20%, measured differentially
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT1
Divide = Bypass
335
490
635
ps
Divide = 2 − 32
375
545
695
ps
Variation with Temperature
0.5
ps/°C
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part, tSKP2
−5
+30
+85
ps
OUT2 to OUT3 on Same Part, tSKP2
15
45
80
ps
All LVPECL OUTs on Same Part, tSKP2
90
130
180
ps
All LVPECL OUTs Across Multiple Parts, tSKP_AB3
275
ps
Same LVPECL OUT Across Multiple Parts, tSKP_AB3
130
ps
LVDS
Termination = 100 Ω differential
Output level 40h (41h) (42h) (43h)<2:1> = 01b
3.5 mA termination current
Output Rise Time, tRL
200
350
ps
20% to 80%, measured differentially
Output Fall Time, tFL
210
350
ps
80% to 20%, measured differentially
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1
Delay off on OUT5 and OUT6
OUT4, OUT5, OUT6, OUT7
Divide = Bypass
0.99
1.33
1.59
ns
Divide = 2 − 32
1.04
1.38
1.64
ns
Variation with Temperature
0.9
ps/°C
OUTPUT SKEW, LVDS OUTPUTS
Delay off on OUT5 and OUT6
OUT4 to OUT7 on Same Part, tSKV2
−85
+270
ps
OUT5 to OUT6 on Same Part, tSKV2
−175
+155
ps
All LVDS OUTs on Same Part, tSKV2
−175
+270
ps
All LVDS OUTs Across Multiple Parts, tSKV_AB3
450
ps
Same LVDS OUT Across Multiple Parts, tSKV_AB3
325
ps
CMOS
B outputs are inverted; termination = open
Output Rise Time, tRC
681
865
ps
20% to 80%; CLOAD = 3 pF
Output Fall Time, tFC
646
992
ps
80% to 20%; CLOAD = 3 pF
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1
Delay off on OUT5 and OUT6
Divide = Bypass
1.02
1.39
1.71
ns
Divide = 2 − 32
1.07
1.44
1.76
ns
Variation with Temperature
1
ps/°C
OUTPUT SKEW, CMOS OUTPUTS
Delay off on OUT5 and OUT6
All CMOS OUTs on Same Part, tSKC2
−140
+145
+300
ps
All CMOS OUTs Across Multiple Parts, tSKC_AB3
650
ps
Same CMOS OUT Across Multiple Parts, tSKC_AB3
500
ps
LVPECL-TO-LVDS OUT
Everything the same; different logic type
Output Skew, tSKP_V
0.74
0.92
1.14
ns
LVPECL to LVDS on same part
LVPECL-TO-CMOS OUT
Everything the same; different logic type
Output Skew, tSKP_C
0.88
1.14
1.43
ns
LVPECL to CMOS on same part
LVDS-TO-CMOS OUT
Everything the same; different logic type
Output Skew, tSKV_C
158
353
506
ps
LVDS to CMOS on same part


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