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SN74GTLPH1612 Datasheet(PDF) 2 Page - Texas Instruments

No. de pieza SN74GTLPH1612
Descripción Electrónicos  18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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SN74GTLPH1612 Datasheet(HTML) 2 Page - Texas Instruments

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DESCRIPTION (CONTINUED)
SN74GTLPH1612
18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES287D – OCTOBER 1999 – REVISED MAY 2005
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and V
CC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use of
pullup or pulldown resistors with the bus-hold circuitry is not recommended.
When V
CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
TSSOP – DGG
Tape and reel
SN74GTLPH1612DGGR
GTLPH1612
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2


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