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CS53L21 Datasheet(PDF) 4 Page - Cirrus Logic |
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CS53L21 Datasheet(HTML) 4 Page - Cirrus Logic |
4 / 66 page 4 DS700PP1 CS53L21 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40 6.2 Power Control 1 (Address 02h) ...................................................................................................... 40 6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 41 6.4 Interface Control (Address 04h) ..................................................................................................... 43 6.5 MIC Control (Address 05h) ............................................................................................................. 44 6.6 ADC Control (Address 06h) ............................................................................................................ 45 6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 47 6.8 SPE Control (Address 09h) ............................................................................................................ 48 6.9 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ................. 49 6.10 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 50 6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 51 6.12 Channel Mixer (Address 18h) ....................................................................................................... 51 6.13 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 52 6.14 ALC Release Rate (Address 1Dh) ................................................................................................ 52 6.15 ALC Threshold (Address 1Eh) ...................................................................................................... 53 6.16 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 54 6.17 Status (Address 20h) (Read Only) ............................................................................................... 55 7. ANALOG PERFORMANCE PLOTS ....................................................................................................56 7.1 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 56 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57 8.1 Auto Detect Enabled ....................................................................................................................... 57 8.2 Auto Detect Disabled ...................................................................................................................... 58 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59 9.1 Power Supply, Grounding ............................................................................................................... 59 9.2 QFN Thermal Pad .......................................................................................................................... 59 10. DIGITAL FILTERS .............................................................................................................................. 60 11. PARAMETER DEFINITIONS .............................................................................................................. 61 12. PACKAGE DIMENSIONS ................................................................................................................. 62 THERMAL CHARACTERISTICS .......................................................................................................... 62 13. ORDERING INFORMATION ............................................................................................................. 63 14. REFERENCES .................................................................................................................................... 63 15. REVISION HISTORY ......................................................................................................................... 64 LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Serial Audio Interface Slave Mode Timing .................................................................................. 15 Figure 4.Serial Audio Interface Master Mode Timing ................................................................................ 15 Figure 5.Control Port Timing - I²C ............................................................................................................. 16 Figure 6.Control Port Timing - SPI Format ................................................................................................ 17 Figure 7.Analog Input Architecture ............................................................................................................ 22 Figure 8.MIC Input Mix w/Common Mode Rejection .................................................................................24 Figure 9.Differential Input .......................................................................................................................... 24 Figure 10.ALC ........................................................................................................................................... 26 Figure 11.Noise Gate Attenuation ............................................................................................................. 27 Figure 12.Signal Processing Engine ......................................................................................................... 28 Figure 13.Master Mode Timing ................................................................................................................. 30 Figure 14.Tri-State Serial Port .................................................................................................................. 31 Figure 15.I²S Format ................................................................................................................................. 31 Figure 16.Left-Justified Format ................................................................................................................. 32 Figure 17.Initialization Flow Chart ............................................................................................................. 33 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34 Figure 19.Control Port Timing, I²C Write ................................................................................................... 35 Figure 20.Control Port Timing, I²C Read ................................................................................................... 35 |
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