Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
CS42888 Datasheet(PDF) 3 Page - Cirrus Logic |
|
CS42888 Datasheet(HTML) 3 Page - Cirrus Logic |
3 / 61 page DS717F1 3 CS42888 5. REGISTER QUICK REFERENCE ......................................................................................................... 38 6. REGISTER DESCRIPTION ................................................................................................................... 40 6.1 Memory Address Pointer (MAP) ..................................................................................................... 40 6.1.1 Increment (INCR) .................................................................................................................. 40 6.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 40 6.2 Chip I.D. and Revision Register (Address 01h) (Read Only) .......................................................... 40 6.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 40 6.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 40 6.3 Power Control (Address 02h) ......................................................................................................... 41 6.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 41 6.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 41 6.3.3 Power Down (PDN) ............................................................................................................... 41 6.4 Functional Mode (Address 03h) ...................................................................................................... 42 6.4.1 DAC Functional Mode (DAC_FM[1:0]) .................................................................................. 42 6.4.2 ADC Functional Mode (ADC_FM[1:0]) .................................................................................. 42 6.4.3 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 42 6.5 Interface Formats (Address 04h) .................................................................................................... 43 6.5.1 Freeze Controls (FREEZE) ................................................................................................... 43 6.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 43 6.5.3 DAC Digital Interface Format (DAC_DIF[2:0]) ....................................................................... 43 6.5.4 ADC Digital Interface Format (ADC_DIF[2:0]) ....................................................................... 44 6.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 44 6.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 44 6.6.2 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 45 6.6.3 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 45 6.6.4 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 45 6.7 Transition Control (Address 06h) .................................................................................................... 45 6.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 45 6.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 46 6.7.3 Auto-Mute (AMUTE) .............................................................................................................. 46 6.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 47 6.8 DAC Channel Mute (Address 07h) ................................................................................................. 47 6.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 47 6.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 47 6.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 47 6.10 DAC Channel Invert (Address 10h) .............................................................................................. 48 6.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 48 6.11 AINX Volume Control (Address 11h-14h) .....................................................................................48 6.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 48 6.12 ADC Channel Invert (Address 17h) .............................................................................................. 48 6.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 49 6.13 When enabled, these bits will invert the signal polarity of their respective channels.Status Control (Address 18h) ....................................................................................................................................... 49 6.13.1 Interrupt Pin Control (INT[1:0]) ............................................................................................ 49 6.14 Status (Address 19h) (Read Only) ................................................................................................ 49 6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR) ........................................................................ 49 6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR) ........................................................................ 50 6.14.3 ADC Overflow (ADCX_OVFL) ............................................................................................. 50 6.15 Status Mask (Address 1Ah) .......................................................................................................... 50 6.16 MUTEC Pin Control (Address 1Bh) .............................................................................................. 50 6.17 MUTEC Polarity Select (MCPOLARITY) ...................................................................................... 50 6.18 MUTE CONTROL ACTIVE (MUTEC ACTIVE) ............................................................................. 50 7. EXTERNAL FILTERS............................................................................................................................ 51 7.1 ADC Input Filter .............................................................................................................................. 51 |
Número de pieza similar - CS42888 |
|
Descripción similar - CS42888 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |