Data Sheet
ATT3000 Series Field-Programmable Gate Arrays
February 1997
6
Lucent Technologies Inc.
I/O Block (continued)
For reliable operation, inputs should have transition
times of less than 100 ns and should not be left float-
ing. Floating CMOS input-pin circuits might be at
threshold and produce oscillations. This can produce
additional power dissipation and system noise. A
typical hysteresis of about 300 mV reduces sensitivity
to input noise. Each user IOB includes a programmable
high-impedance pull-up resistor which is selected by
the program to provide a constant high for otherwise
undriven package pins. Normal CMOS handling
precautions should be observed.
Flip-flop loop delays for the IOB and logic block flip-
flops are approximately 3 ns. This short delay provides
good performance under asynchronous clock and data
conditions. Short loop delays minimize the probability
of a metastable condition which can result from asser-
tion of the clock during data transitions. Because of the
short loop delay characteristic in the FPGA, the IOB
flip-flops can be used to synchronize external signals
applied to the device. When synchronized in the IOB,
the signals can be used internally without further con-
sideration of their clock relative timing, except as it
applies to the internal logic and routing path delays.
Output buffers of the IOBs provide CMOS-compatible
4 mA source-or-sink drive for high fan-out CMOS or
TTL compatible signal levels. The network driving IOB
pin .o becomes the registered or direct data source for
the output buffer. The 3-state control signal (IOB pin .t)
can control output activity. An open-drain type output
may be obtained by using the same signal for driving
the output and 3-state signal nets so that the buffer out-
put is enabled only for a LOW.
Configuration program bits for each IOB control
features such as optional output register, logical signal
inversion, and 3-state and slew rate control of the out-
put.
The program-controlled memory cells in Figure 3
control the following options:
s
Logical inversion of the output is controlled by one
configuration program bit per IOB.
s
Logical 3-state control of each IOB output buffer is
determined by the states of configuration program
bits which turn the buffer on or off or select the output
buffer 3-state control interconnection (IOB pin .t).
When this IOB output control signal is high, a logic 1,
the buffer is disabled and the package pin is high
impedance. When this IOB output control signal is
low, a logic 0, the buffer is enabled and the package
pin is active. Inversion of the buffer 3-state control
logic sense (output enable) is controlled by an addi-
tional configuration program bit.
s
Direct or registered output is selectable for each IOB.
The register uses a positive-edge, clocked flip-flop.
The clock source may be supplied (IOB pin .ok) by
either of two metal lines available along each die
edge. Each of these lines is driven by an invertible
buffer.
s
Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce
capacitive load peak currents of noncritical outputs
and minimize system noise.
s
A high-impedance pull-up resistor may be used to
prevent unused inputs from floating.
Summary of I/O Options
s
Inputs
—Direct
—Flip-flop/latch
—CMOS/TTL threshold (chip inputs)
—Pull-up resistor/open circuit
s
Outputs
—Direct/registered
—Inverted/not
—3-state/on/off
—Full speed/slew limited
—3-state/output enable (inverse)
