Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
s
High performance:
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
s
User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system
logic changes
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Flexible array architecture:
— Compatible arrays ranging from 1500 to
6000 gate logic complexity
— Extensive register, combinatorial, and I/O
capabilities
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator amplifier
s
Standard product availability:
— Low-power 0.55 µm CMOS, static memory
technology
— Pin-for-pin compatible with Xilinx* XC3000*
and XC3100* families
— Cost-effective for volume production
— 100% factory pretested
— Selectable configuration modes
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ORCA™ Foundry for ATT3000 Development
System support
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All FPGAs processed on a QML-certified line
s
Extensive packaging options
Description
The CMOS ATT3000 Series Field-Programmable
Gate Array (FPGA) family provides a group of high-
density, digital integrated circuits. Their regular,
extendable, flexible, user-programmable array
architecture is composed of a configuration program
store plus three types of configurable elements: a
perimeter of I/O blocks, a core array of logic blocks,
and resources for interconnection. The general struc-
ture of an FPGA is shown in Figure 1.
The ORCA Foundry for ATT3000 Development Sys-
tem provides automatic place and route of netlists.
Logic and timing simulation are available as design
verification alternatives. The design editor is used for
interactive design optimization and to compile the
data pattern that represents the configuration pro-
gram.
The FPGA’s user-logic functions and interconnec-
tions are determined by the configuration program
data stored in internal static memory cells. The pro-
gram can be loaded in any of several modes to
accommodate various system requirements. The
program data resides externally in an EEPROM,
EPROM, or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of pro-
gram data at powerup. A serial configuration PROM
can provide a very simple serial configuration pro-
gram storage.
*
Xilinx, XC3000, and XC3100 are registered trademarks of
Xilinx, Inc.
Table 1. ATT3000 Series FPGAs
FPGA
Max
Logic
Gates
Typical Gate
Range
Configurable
Logic
Blocks
Array
User I/Os
Max
Flip-
Flops
Horizontal
Long Lines
Configuration
Data Bits
ATT3020
1,500
1,000—1,500
64
8 x 8
64
256
16
14,779
ATT3030
2,000
1,500—2,000
100
10 x 10
80
360
20
22,176
ATT3042
3,000
2,000—3,000
144
12 x 12
96
480
24
30,784
ATT3064
4,500
3,500—4,500
224
16 x 14
120
688
32
46,064
ATT3090
6,000
5,000—6,000
320
20 x 16
144
928
40
64,160
