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IRMCK201

 High Performance Configurable Digital AC Servo Control IC ( 62 Page)


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IRMCK201
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
6
List of Figures
Figure 1.
Basic Block Diagram of IRMCK201............................................................................................................. 7
Figure 2.
Detailed Block Diagram of IRMCK201 ........................................................................................................ 8
Figure 3.
Input/Output of IRMCK201 .......................................................................................................................... 9
Figure 4.
Typical Connection of IRMCK201.............................................................................................................. 13
Figure 5.
Oscillator Circuit.......................................................................................................................................... 14
Figure 6.
PLL Low Pass Filter Shielding .................................................................................................................... 15
Figure 7.
System Level SYNC-to-SYNC Timing ....................................................................................................... 23
Figure 8.
FAULT and REDLED Response to GATEKILL ........................................................................................ 24
Figure 9.
SPI Timing................................................................................................................................................... 25
Figure 10.
Host Parallel Read Cycle Timing............................................................................................................... 26
Figure 11.
Host Parallel Write Cycle Timing.............................................................................................................. 27
Figure 12.
Discrete I/O Timing ................................................................................................................................... 28
Figure 13.
PWM Timing ............................................................................................................................................. 29
Figure 14.
IR2175 Interface ........................................................................................................................................ 29
Figure 15.
Encoder Timing ......................................................................................................................................... 30
Figure 16.
Top Level ADC Timing............................................................................................................................. 31
Figure 17.
ADC Specific Timing ................................................................................................................................ 32
List of Tables
Table 1: Typical Values for the Clock Circuit ................................................................................................................ 14
Table 2: PLL Test Pin Assignments................................................................................................................................ 15
Table 3: PLL Low Pass Filter Values ............................................................................................................................. 16
Table 4: Absolute Maximum Ratings ............................................................................................................................. 17
Table 5: Recommended Operating Conditions ............................................................................................................... 17
Table 6: DC Characteristics ............................................................................................................................................ 18
Table 7: Non Schmitt Trigger Input Characteristics ....................................................................................................... 18
Table 8: Schmitt Trigger Input Characteristics ............................................................................................................... 18
Table 9: Output Characteristics....................................................................................................................................... 18
Table 10: Output Characteristics OSC2CLK .................................................................................................................. 19
Table 11 .......................................................................................................................................................................... 20
Table 12: Pin and I/O Characteristics ............................................................................................................................. 22
Table 13: IRMCK201 Power Consumption.................................................................................................................... 22
Table 14: System Level SYNC-to-SYNC Timing .......................................................................................................... 24
Table 15: FAULT and REDLED Response to GATEKILL ........................................................................................... 24
Table 16: SPI Timing ...................................................................................................................................................... 25
Table 17: Host Parallel Read Cycle Timing.................................................................................................................... 26
Table 18: Host Parallel Write Cycle Timing................................................................................................................... 27
Table 19: Discrete I/O Timing ........................................................................................................................................ 28
Table 20: PWM Timing .................................................................................................................................................. 29
Table 21: IR2175 Interface ............................................................................................................................................. 29
Table 22: Encoder Timing .............................................................................................................................................. 30
Table 23: Top Level ADC Timing.................................................................................................................................. 31
Table 24: ADC Specific Timing ..................................................................................................................................... 32
Table 25: PLL Electrical Characteristics......................................................................................................................... 33
Table 26: QFP100 Package............................................................................................................................................. 60
Table 27: QFP100 Dimensions ....................................................................................................................................... 61
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