K6E1004C1B datasheet(6/9 Pages) SAMSUNG | 256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out

6 page

K6E1004C1B-C/B-L

CMOS SRAM

PRELIMINARY

Rev. 3.0

- 6 -

July 1998

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured

±200mV space from steady state voltage with Load(B). This parameter is sampled and not 100%

tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

Address

tWP(2)

tDW

tDH

Valid Data

Data in

Data out

tWC

tWR(5)

tAW

tCW(3)

High-Z(8)

High-Z

tOHZ(6)

tAS(4)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

Address

tWP1(2)

tDW

tDH

tOW

tWHZ(6)

Valid Data

Data in

Data out

tWC

tAS(4)

tWR(5)

tAW

tCW(3)

(10)

(9)

High-Z(8)

High-Z

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