BUK101-50DL datasheet(6/10 Pages) PHILIPS

No. de pieza	BUK101-50DL

Descripción Electrónicos	PowerMOS transistor Logic level TOPFET

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Philips Semiconductors

Product specification

PowerMOS transistor

BUK101-50DL

Logic level TOPFET

Fig.6. Typical on-state characteristics, T

j = 25 ˚C.

ID = f(V

DS); parameter VIS; tp = 2 ms

Fig.7. Typical on-state resistance, T

j = 25 ˚C.

R

DS(ON) = f(ID); parameter VIS; tp = 2 ms

Fig.8. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 13 A; VIS = 5 V

Fig.9. Typical overload protection characteristics.

t

d sc = f(PDS); conditions: VIS ≥ 4 V; Tj = 25 ˚C.

Fig.10. Normalised limiting overload dissipation.

P

DSM% =100⋅PDSM/PDSM(25 ˚C) = f(Tmb)

Fig.11. Typical overload protection characteristics.

Conditions: V

DD = 13 V; VIS = 5 V; SC load = 30 mΩ

0

2

4

VDS / V

ID / A

BUK101-50DL

50

40

30

20

10

0

13

5

VIS / V =

6

5.5

5

4.5

4

3.5

3

0.1

1

10

PDS / kW

td sc / ms

BUK101-50DL

100

10

1

0.1

PDSM

0

20

40

ID / A

RDS / mOhm

BUK101-50DL

120

100

80

60

40

20

0

VIS / V =

4.5

5

5.5

6

4

3.5

-60

-40

-20

0

20

40

60

80

100

120

140

Tmb / C

PDSM%

120

100

80

60

40

20

0

-60

-40

-20

0

20

40

60

80

100 120 140

Tj / C

a

Normalised RDS(ON) = f(Tj)

1.5

1.0

0.5

0

-60

-20

20

60

100

140

180

220

Tmb / C

BUK101-50DL

1

0.5

0

Energy / J

Time / ms

Tj(TO)

Energy & Time

April 1993

6

Rev 1.100

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