TLC1550I, TLC1550M, TLC1551I

10BIT ANALOGTODIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043G − MAY 1991 − REVISED NOVEMBER 2003

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.†

NO.‡

DESCRIPTION

ANLG GND

4

3

Analog ground. The reference point for the voltage applied on terminals ANLG VDD, AIN, REF+, and REF−.

AIN

5

4

Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.

ANLG VDD

6

5

Analog positive power supply voltage. The voltage applied to this terminal is designated VDD3.

CLKIN

26

22

Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a

few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high

or left unconnected.

CS

25

21

Chip-select. CS must be low for RD or WR to be recognized by the A/D converter.

D0

13

11

Data bus output. D0 is bit 1 (LSB).

D1

14

12

Data bus output. D1 is bit 2.

D2

16

13

Data bus output. D2 is bit 3.

D3

17

14

Data bus output. D3 is bit 4.

D4

18

15

Data bus output. D4 is bit 5.

D5

19

16

Data bus output. D5 is bit 6.

D6

20

17

Data bus output. D6 is bit 7.

D7

21

18

Data bus output. D7 is bit 8.

D8

23

19

Data bus output. D8 is bit 9.

D9

24

20

Data bus output. D9 is bit 10 (MSB).

DGTL GND1

7

6

Digital ground 1. The ground for power supply DGTL VDD1 and is the substrate connection

DGTL GND2

9

7

Digital ground 2. The ground for power supply DGTL VDD2

DGTL VDD1

10

8

Digital positive power-supply voltage 1. DGTL VDD1 supplies the logic. The voltage applied to DGTL VDD1 is

designated VDD1.

DGTL VDD2

11

9

Digital positive power-supply voltage 2. DGTL VDD2 supplies only the higher-current output buffers. The voltage

applied to DGTL VDD2 is designated VDD2.

EOC

12

10

End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred

to the output latch. EOC can be connected to the

µP- or DSP-interrupt terminal or can be continuously polled.

RD

28

24

Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The

output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD

resets EOC to a high within the td(EOC) specifications.

REF+

2

1

Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts

to 1111111111. Analog input voltages between REF + and REF − convert to the appropriate result in a ratiometric

manner.

REF −

3

2

Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF − converts

to 0000000000.

WR

27

23

Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds

the analog input until conversion is completed. Before and after the conversion period, which is given by t conv,

the ADC remains in the sampling mode.

† Terminal numbers for FK and FN packages.

‡ Terminal numbers for J, DW, and NW packages.