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SN74LV125ADBR Datasheet(PDF) 4 Page - Texas Instruments |
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SN74LV125ADBR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 19 page SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3STATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 5) SN54LV125A SN74LV125A UNIT MIN MAX MIN MAX UNIT VCC Supply voltage 2 5.5 2 5.5 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 V VIH High-level input voltage VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 V VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 V VIL Low-level input voltage VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 V VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3 VI Input voltage 0 5.5 0 5.5 V VO Output voltage High or low state 0 VCC 0 VCC V VO Output voltage 3-state 0 5.5 0 5.5 V VCC = 2 V −50 −50 µA IOH High-level output current VCC = 2.3 V to 2.7 V −2 −2 IOH High-level output current VCC = 3 V to 3.6 V −8 −8 mA VCC = 4.5 V to 5.5 V −16 −16 mA VCC = 2 V 50 50 µA IOL Low-level output current VCC = 2.3 V to 2.7 V 2 2 IOL Low-level output current VCC = 3 V to 3.6 V 8 8 mA VCC = 4.5 V to 5.5 V 16 16 mA VCC = 2.3 V to 2.7 V 200 200 ∆t/∆v Input transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V ∆t/∆v Input transition rise or fall rate VCC = 4.5 V to 5.5 V 20 20 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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