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CS3842AGDR8 Datasheet(PDF) 6 Page - ON Semiconductor

No. de pieza CS3842AGDR8
Descripción Electrónicos  Off-Line Current Mode PWM Control Circuit with Undervoltage Lockout
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS3842AGDR8 Datasheet(HTML) 6 Page - ON Semiconductor

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CS2842A, CS3842A, CS2843A, CS3843A
http://onsemi.com
6
Figure 4. Test Circuit
VREF
VCC
VOUT
GND
COMP
VFB
Sense
OSC
0.1 μF
0.1 μF
RT
1.0 kΩ
1.0 W
2N2222
100 kΩ
VCC
VREF
VOUT
GND
A
5.0 kΩ
Sense
ADJUST
CT
4.7 kΩ
4.7 kΩ
1.0 kΩ
ERROR AMP
ADJUST
CIRCUIT DESCRIPTION
CSX843A
8.4 V
7.6 V
CSX842A
16 V
10 V
VON
VOFF
ON/OFF Command
to reset of IC
VCC
< 1.0 mA
< 15 mA
VON VOFF
VCC
ICC
Figure 5. Typical Undervoltage Characteristics
Undervoltage Lockout
During Undervoltage Lockout (Figure 5), the output
driver is biased to a high impedance state. The output should
be shunted to ground with a resistor to prevent output
leakage current from activating the power switch.
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal which
represents the peak output inductor current (Figure 6). An
increase in VCC causes the inductor current slope to increase,
thus reducing the duty cycle. This is an inherent feed−forward
characteristic of current mode control, since the control
voltage does not have to change during changes of input
supply voltage.
Figure 6. Timing Diagram for Key CS2841B
Parameters
Switch
Current
EA Output
VCC
IO
VO
OSC
RESET
OSC
When the power supply sees a sudden large output current
increase, the control voltage will increase allowing the duty
cycle to momentarily increase. Since the duty cycle tends to
exceed the maximum allowed to prevent transformer
saturation in some power supplies, the internal oscillator
waveform provides the maximum duty cycle clamp as
programmed by the selection of oscillator components.
Setting the Oscillator
Oscillator timing capacitor, CT, is charged by VREF
through RT and discharged by an internal current source.
During the discharge time, the internal clock signal blanks
out the output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times are
determined by the formula:


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