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74VCXF16283_0011 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74VCXF16283_0011 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Truth Table H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 2: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 3: Output level before the indicated steady-state input conditions were established. Logic Diagram Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input I1 - I18 Data Inputs O1 - O18 3-STATE Outputs Inputs Outputs OE LE CLK In On H XXX Z LH X L L LH X H H LL ↑ LL LL ↑ HH LL H X O0 (Note 2) LLL X O0 (Note 3) |
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