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MC100EP809FAG Datasheet(PDF) 2 Page - ON Semiconductor |
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MC100EP809FAG Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 9 page MC100EP809 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI 0 VCCO). Figure 1. 32−Lead LQFP Pinout (Top View) Q2 VCCO Q2 Q1 Q1 Q0 Q0 VCCO VCCO Q6 Q6 Q7 Q7 Q8 Q8 VCCO MC100EP809 Table 1. PIN DESCRIPTION PIN FUNCTION HSTL_CLK*, HSTL_CLK** HSTL or LVDS Differential Inputs LVPECL_CLK*, LVPECL_CLK** LVPECL Differential Inputs CLK_SEL** LVCMOS/LVTTL Input CLK Select OE** LVCMOS/LVTTL Output Enable Q0 − Q8, Q0 − Q8 HSTL Differential Outputs VCC1 Positive Supply_Core (3.0 V − 3.6 V) VCC0 Positive Supply_HSTL Outputs (1.6 V − 2.0 V) GND Ground * Pins will default LOW when left open. ** Pins will default HIGH when left open. Table 2. TRUTH TABLE OE* CLK_SEL Q0 − Q8 Q0 − Q8 L L L H L H L H H L HSTL_CLK HSTL_CLK H H LVPECL_CLK LVPECL_CLK *The OE (Output Enable) signal is synchronized with the rising edge of the HSTL_CLK and LVOCL_CLK signals. |
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