SN65LVDS048A_06 datasheet(2/11 Pages) TI | LVDS QUAD DIFFERENTIAL LINE RECEIVER

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TRUTH TABLE

(1)

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

7 V

300 k

Ω

300 k

Ω

Input

VCC

Ω

300 k

Ω

VCC

7 V

EN,EN

Ω

VCC

7 V

Output

ABSOLUTE MAXIMUM RATINGS

SN65LVDS048A

SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DIFFERENTIAL INPUT

ENABLES

OUTPUT

RIN+– RIN–

ROUT

VID ≥ 100 mV

L or

VID ≤ –100 mV

OPEN

Open/short or terminated

All other conditions

(1)

H = high level, L = low level, X = irrelevant, Z = high impedance

(off)

over operating free-air temperature range (unless otherwise noted)(1)(2)

UNIT

VCC

Supply voltage range

–0.3 V to 4 V

VI(RIN+,

Input voltage range

–0.3 V to 4 V

RIN-)

Enable input voltage (EN, EN )

–0.3 V to (VCC +0.3 V)

VO(ROUT)

Output voltage

–0.3 V to (VCC +0.3 V)

Bus-pin (RIN+, RIN–) electrostatic discharge(3)

> 10 kV

Continuous power dissipation

See Dissipation Rating Table

Storage temperature range

–65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3)

Tested in accordance with MIL-STD-883C Method 3015.7.

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