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CAT24WC129L-1.8TE13 Datasheet(PDF) 4 Page - Catalyst Semiconductor |
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CAT24WC129L-1.8TE13 Datasheet(HTML) 4 Page - Catalyst Semiconductor |
4 / 9 page Discontinued Part CAT24WC129 4 Doc. No. 1079, Rev. V Figure 3. Start/Stop Timing Figure 2. Write Cycle Timing Figure 1. Bus Timing START BIT SDA STOP BIT SCL tWR STOP CONDITION START CONDITION ADDRESS ACK 8TH BIT BYTE n SCL SDA tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH I2C BUS PROTOCOL The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC129 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. PIN DESCRIPTIONS SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to Vcc, the top 1/4 array of memory (locations 3000H to 3FFFH) is write protected. When left floating, memory is unprotected. |
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