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MC100LVEL91DW Datasheet(PDF) 1 Page - ON Semiconductor

No. de pieza MC100LVEL91DW
Descripción Electrónicos  3.3 V Triple LVPECL Input to ??.3 V to ??.0 V ECL Output Translator
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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MC100LVEL91DW Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 10
1
Publication Order Number:
MC100LVEL91/D
MC100LVEL91
3.3 V Triple LVPECL Input to
−3.3 V to −5.0 V ECL Output
Translator
Description
The MC100LVEL91 is a triple LVPECL input to ECL output
translator. The device receives low voltage differential PECL signals,
determined by the VCC supply level, and translates them to differential
−3.3 V to −5.0 V ECL output signals.
To accomplish the level translation the LVEL91 requires three
power rails. The VCC supply should be connected to the positive
supply, and the VEE pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
VEE and VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. This condition will force the
Q output to a low, ensuring stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
620 ps Typical Propagation Delay
The 100 Series Contains Temperature Compensation
Operating Range: VCC = 3.8 V to 3.0 V;
VEE = −3.0 V to −5.5 V; GND = 0 V
Q Output will Default LOW with Inputs Open or at GND
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAM*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= Pb−Free Package
SO−20
DW SUFFIX
CASE 751D
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
20
1
MC100LVEL91
AWLYYWWG
1


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