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CAT24WC6633WI-1.8T3C Datasheet(PDF) 3 Page - Catalyst Semiconductor

No. de pieza CAT24WC6633WI-1.8T3C
Descripción Electrónicos  64K-bit I2C Serial EEPROM with Partial Array Write Protection
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Fabricante Electrónico  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

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CAT24WC66
© 2006 Catalyst Semiconductor, Inc.
3
Doc. No. 1037 Rev. J
Characteristics subject to change without notice
AC CHARACTERISTICS
VCC = 1.8V to 5.5V, unless otherwise specified. Output Load is 1TTL Gate and 100pF.
Memory Read & Write Cycle Limits
1.8V - 2.5V
4.5V - 5.5V
Units
Symbol
Parameter
Min
Max
Min
Max
FSCL
Clock Frequency
100
400
kHz
TI
(1)
Noise Suppression Time Constant at
SCL, SDA Inputs
200
200
ns
tAA
SCL Low to SDA Data Out and ACK Out
3.5
1
µs
tBUF
(1)
Time the Bus Must be Free Before a
New Transmission Can Start
4.7
1.2
µs
tHD:STA
Start Condition Hold Time
4
0.6
µs
tLOW
Clock Low Period
4.7
1.2
µs
tHIGH
Clock High Period
4
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
50
50
ns
tR
(1)
SDA and SCL Rise Time
1
0.3
µs
tF
(1)
SDA and SCL Fall Time
300
300
ns
tSU:STO
Stop Condition Setup Time
4
0.6
µs
tDH
Data Out Hold Time
100
100
ns
Power-Up Timing
(1) (2)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-Up to Read Operation
1
ms
tPUW
Power-Up to Write Operation
1
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to
remain high, and the device does not respond to its
slave address.


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