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SN75423, SN75424 HIGH-VOLTAGE HIGH-CURRENT DARLINGTON TRANSISTOR ARRAYS SLDS115 – FEBRUARY 1998 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, TA = 25°C (unless otherwise noted) PARAMETER TEST TEST CONDITIONS SN75423 SN75424 UNIT PARAMETER TEST FIGURE TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT IC = 125 mA 5 IC = 200 mA 2.4 6 VI( ) On state input voltage 5 VCE =2V IC = 250 mA 2.7 V VI(on) On-state input voltage 5 VCE = 2 V IC = 275 mA 7 V IC = 300 mA 3 IC = 350 mA 8 C ll t itt II = 250 µA, IC = 100 mA 0.9 1.1 0.9 1.1 VCE(sat) Collector-emitter saturation voltage 6 II = 350 µA, IC = 200 mA 1 1.3 1 1.3 V () saturation voltage II = 500 µA, IC = 350 mA 1.2 1.6 1.2 1.6 VF Clamp-diode forward voltage 8 IF = 350 mA 1.7 2 1.7 2 V Collector cutoff 1 VCE = 100 V, II = 0 100 100 ICEX Collector cutoff current 2 VCE = 100 V, VI = 1 V, 500 µA current 2 CE , TA = 70°C VI 1 V, 500 II( ff) Off state input current 3 VCE = 100 V, IC = 500 µA, 50 65 50 65 µA II(off) Off-state input current 3 CE , TA = 70°C C µ , 50 65 50 65 µA VI = 3.85 V 0.93 1.35 II(on) Input current 4 VI = 5 V 0.35 0.5 mA () VI = 12 V 1 1.45 IR Clamp-diode reverse current 7 VR = 100 V 50 50 µA Ci Input capacitance VI = 0, f = 1 MHz 15 30 15 30 pF switching characteristics, TA = 25°C free-air temperature PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output VS = 50 V, See Figure 9 RL = 163 Ω, CL = 15 pF, 130 ns tPHL Propagation delay time, high-to-low-level output VS = 50 V, See Figure 9 RL = 163 Ω, CL = 15 pF, 20 ns VOH High-level output voltage after switching VS = 60 V, IO ≈ 300 mA, See Figure 10 VS –20 mV |
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