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| SG3526_06 |
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6 page 
SG3526 http://onsemi.com 6 Figure 8. VC Saturation Voltage as a Function of Sink Current Figure 9. Oscillator Period Figure 10. Error Amplifier Figure 11. Undervoltage Lockout Figure 12. Pulse Processing Logic The metering Flip−Flop is an asynchronous data latch which suppresses high frequency oscillations by allowing only one PWM pulse per oscillator cycle. The memory Flip−Flop prevents double pulsing in a push−pull configuration by remembering which output produced the last pulse. 2.0 5.0 10 20 50 100 200 IC, SINK CURRENT (mA) OSCILLATOR PERIOD (ms) RD = 0 Ω VCC Q6 Q5 Vref 125 μA Q3 Q4 50 μA Q8 Q9 500 1.0k Q2 1 + Error − Error Q10 3 Compensation Q12 Q11 Q7 50 μA 14 μA Q1 1.0k 500 100 μA 14 μA 100 μA 100 μA Vref R1 1.2V Bandgap Reference R2 + − To Reset To Driver A To Driver B Metering F/F S D Q Q Q R S Clock PWM PWM Sync Memory F/F 2.5 2.0 1.5 1.0 0.5 0 200 100 50 20 10 5.0 2.0 |
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