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CDP68HC68T1MZ Datasheet(PDF) 9 Page - Intersil Corporation

No. de pieza CDP68HC68T1MZ
Descripción Electrónicos  CMOS Serial Real-Time Clock With RAM and Power Sense/Control
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Fabricante Electrónico  INTERSIL [Intersil Corporation]
Página de inicio  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP68HC68T1MZ Datasheet(HTML) 9 Page - Intersil Corporation

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9
FN1547.7
March 17, 2006
Power Sensing (See Figure 3)
When Power Sensing is enabled (Bit 5 = 1 in Interrupt
Control Register), AC transitions are sensed at the LINE input
pin. Threshold detectors determine when transitions cease.
After a delay of 2.68ms to 4.64ms, plus the external input
circuit RC time constant, an interrupt is generated and a bit is
set in the Status Register. This bit can then be sampled to see
if system power has turned back on. See PIN FUNCTIONS,
LINE PIN. The power-sense circuitry operates by sensing the
level of the voltage presented at the line input pin. This voltage
is centered around VDD and as long as it is either plus or
minus a threshold (about 1V) from VDD a power-sense failure
will not be indicated. With an AC signal present, remaining in
this VDD window longer than a minimum of 2.68ms will
activate the power-sense circuit. The larger the amplitude of
the AC signal, the less time it spends in the VDD window, and
the less likely a power failure will be detected. A 60Hz, 10VP-P
sinewave voltage is an applicable signal to present at the
LINE input pin to setup the power sense function.
Power Down (See Figure 4)
Power down is a processor-directed operation. A bit is set in
the Interrupt Control Register to initiate operation. 3 pins are
affected. The PSE (Power Supply Enable) output, normally
high, is placed low. The CLK OUT is placed low. The CPUR
output, connected to the processors reset input is also
placed low. In addition, the Serial Interface is disabled.
Power Up (See Figures 5 and 6)
Two conditions will terminate the Power-Down mode. The
first condition (See Figure 5) requires an interrupt. The
interrupt can be generated by the alarm circuit, the
programmable periodic interrupt signal, or the power sense
circuit.
The second condition that releases Power Down occurs
when the level on the VSYS pin rises about 1.0V above the
level at the VBATT input, after previously falling to the level of
VBATT (See Figure 6) in the Battery Backup Mode or VSYS
falls to logic low and returns high in the Single Supply Mode.
FIGURE 3. POWER-SENSING FUNCTIONAL DIAGRAM
FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM
FIGURE 5. POWER-UP FUNCTIONAL DIAGRAM (INITIATED
BY INTERRUPT SIGNAL
XTAL IN
XTAL OUT
LINE
VDD
REAL-TIME CLOCK
CDP68HC68T1
STATUS REGISTER
INT
INT
CPU
CDP68HC05C16B
VDD
0V
I
VSYS
INTERRUPT
CONTROL
REGISTER
I
SERIAL
INTERFACE
CLK
OUT
CPUR
REAL-TIME CLOCK
CDP68HC68T1
PSE
OSC
RESET
CPU
CDP68HC05C4B
MISO
MOSI
FROM SYSTEM
POWER
TO SYSTEM
POWER CONTROL
POWER
SENSE
OR
ALARM
CIRCUIT
SERIAL
INTERFACE
PERIODIC
INTERRUPT
SIGNAL
POWER
UP
REAL-TIME CLOCK
CDP68HC68T1
PSE
CPUR
CLK
OUT
INT
MISO
MOSI


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