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74ABT374 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74ABT374 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 13 page ©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ABT374 Rev. 1.4 2 Connection Diagram Pin Descriptions Functional Description The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are com- mon to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the con- tents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input (Active Rising Edge) OE 3-STATE Output Enable Input (Active LOW) O0–O7 3-STATE Outputs Inputs Internal Outputs Function OE CP D Q O H H L NC Z Hold H H H NC Z Hold H L L Z Load H H H Z Load L L L L Data Available L H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data |
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