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DM74ALS646WM Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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DM74ALS646WM Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 6 page www.fairchildsemi.com 4 Switching Characteristics over recommended operating free air temperature range Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. Symbol Parameter Conditions From (Input) Min Max Units To (Output) tPLH Propagation Delay Time VCC = 4.5V to 5.5V, CBA or CAB 10 30 ns LOW-to-HIGH Level Output CL = 50 pF, to A or B tPHL Propagation Delay Time R1 = R2 = 500Ω,CBA or CAB 517 ns HIGH-to-LOW Level Output TA = Min to Max to A or B tPLH Propagation Delay Time A or B to 520 ns LOW-to-HIGH Level Output B or A tPHL Propagation Delay Time A or B to 312 ns HIGH-to-LOW Level Output B or A tPLH Propagation Delay Time SBA or SAB LOW-to-HIGH Level Output to A or B 12 35 ns (with A or B LOW) (Note 5) tPHL Propagation Delay Time SBA or SAB HIGH-to-LOW Level Output to A or B 5 20 ns (with A or B LOW) (Note 5) tPLH Propagation Delay Time SBA or SAB LOW-to-HIGH Level Output to A or B 6 25 ns (with A or B HIGH) (Note 5) tPHL Propagation Delay Time SBA or SAB HIGH-to-LOW Level Output to A or B 5 20 ns (with A or B HIGH) (Note 5) tPZH Output Enable Time G to 317 ns to HIGH Level Output A or B tPZL Output Enable Time G to 520 ns to LOW Level Output A or B tPHZ Output Disable Time G to 110 ns from HIGH Level Output A or B tPLZ Output Disable Time G to 216 ns from LOW Level Output A or B tPZH Output Enable Time DIR to 630 ns to HIGH Level Output A or B tPZL Output Enable Time DIR to 525 ns to LOW Level Output A or B tPHZ Output Disable Time DIR to 110 ns from HIGH Level Output A or B tPLZ Output Disable Time DIR to 216 ns from LOW Level Output A or B |
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