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ISL6123 Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL6123 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 21 page 6 FN9005.8 February 5, 2007 Descriptions and Operation The ISL612X sequencer family consists of several four channel voltage sequencing controllers in various functional and personality configurations. All are designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD +5.3V (VQP) in a user programmed sequence. With the four-channel ISL6123 the ENABLE must be asserted high and all four voltages to be sequenced must be above their respective user programmed Under Voltage Lock Out (UVLO) levels before programmed output turn on sequencing can begin. Sequencing and delay determination is accomplished by the choice of external cap values on the DLY_ON and DLY_OFF pins. Once all four UVLO inputs and ENABLE are satisfied for 10ms, the four DLY_ON caps are simultaneously charged with 1µA current sources to the DLY_Vth level of 1.27V. As each DLY_ON pin reaches the DLY_Vth level its associated GATE will then turn-on with a 1µA source current to the VQP voltage of VDD+5.3V. Thus all four GATEs will sequentially turn on. Once at DLY_Vth the DLY_ON pins will discharge to be ready when next needed. After the entire turn on sequence has been completed and all GATEs have reached the charge pumped voltage (VQP), a 160ms delay is started to ensure stability after which the RESET# output will be released to go high. Subsequent to turn-on, if any input falls below its UVLO point for longer than the glitch filter period (~30 μs) this is considered a fault. RESET# and SYSRST# are pulled low and all GATEs are simultaneously also pulled low. In this mode the GATEs are pulled low with 88mA. Normal shutdown mode is entered when no UVLO is violated and the ENABLE is deasserted. When ENABLE is deasserted, RESET# is asserted and pulled low. Next, all four shutdown ramp caps on the DLY_OFF pins are charged with a 1 μA source and when any ramp-cap reaches DLY_Vth, a latch is set and a current is sunk on the respective GATE pin to turn off its external MOSFET. When the GATE voltage is approximately 0.6V, the GATE is pulled down the rest of the way at a higher current level. Each individual external FET is thus turned off removing the voltages from the load in the programmed sequence. SYSRST# Pull-Up Voltage Vpu_srst VDD V SYSRST# Pull-Down Current Ipu_1.5 VDD = 1.5V 5 μA Ipu_5 VDD = 5V 100 μA SYSRST# Low Output Voltage Vol_srst VDD = 1.5V, IOUT = 100μA150 mV SYSRST# Output Capacitance Cout_srst 10 pF SYSRST# Low to GATE Turn-Off TdelSYS_G GATE = 80% of VDD+5V 40 ns GATE GATE Turn-On Current IGATEon GATE = 0V 0.8 1.1 1.4 μA GATE Turn-Off Current IGATEoff_l GATE = VDD, Disabled -1.4 -1.05 -0.8 μA GATE Current Range IGATE_range Within IC IGATE max-min 0.35 μA GATE Turn-On/Off Current Temp. Coeff. TC_IGATE 0.2 nA/°C GATE Pull-Down High Current IGATEoff_h GATE = VDD, UVLO = 0V 88 mA GATE High Voltage VGATEh VDD < 2V, TJ = +25°C VDD+4.9V V VGATEh VDD > 2V VDD+5V VDD+5.3V V GATE Low Voltage VGATEl Gate Low Voltage, VDD = 1V 0 0.1 V BIAS IC Supply Current IVDD_5V VDD = 5V 0.20 0.5 mA IVDD_3.3V VDD = 3.3V 0.14 mA IVDD_1.5V VDD = 1.5V 0.10 mA ISL6123, ISL6130 Stand By IC Supply Current IVDD_sb VDD = 5V, ENABLE = 0V 1 μA VDD Power On Reset VDD_POR 1 V Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 |
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