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CDCL6010RGZR Datasheet(PDF) 2 Page - Texas Instruments

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No. de pieza CDCL6010RGZR
Descripción Electrónicos  1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

CDCL6010RGZR Datasheet(HTML) 2 Page - Texas Instruments

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DESCRIPTION
CDCL6010
SLLS780 – FEBRUARY 2007
The CDCL6010 is a high-performance, low phase
The CDCL6010 supports one differential LVDS clock
noise clock multiplier, distributor, jitter cleaner, and
input and a total of 11 differential CML outputs. One
low skew buffer. It effectively cleans a noisy system
output is a straight bypass with no support for jitter
clock with a fully-integrated low noise Voltage
cleaning or clock multiplication. The remaining 10
Controlled Oscillator (VCO) that operates in the
outputs are available in two groups of five outputs
1.2GHz–1.275GHz
range.
(Note
that
the
LC
each with independent frequency division ratios.
oscillator oscillates in the 2.4GHz–2.55GHz range.
Those 10 outputs can be optionally setup to bypass
The frequency is predivided by 2 before
the
the PLL when no jitter cleaning is needed. The CML
post-dividers P0 and P1.)
outputs are compatible with LVDS receivers if
ac-coupled.
The output frequency (FOUT) is synchronized to the
frequency of the input clock (FIN). The programmable
With careful observation of the input voltage swing
pre-dividers, M and N, and the post-dividers, P0 and
and common-mode voltage limits, the CDCL6010
P1, give a high flexibility to the ratio of the output
can support a single-ended clock input as outlined in
frequency to the input frequency:
the Pin Description Table.
FOUT = FIN × N/(M × P)
The CDCL6010 can operate as a multi-output clock
buffer in a PLL bypass mode.
Where:
P (P0, P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80
All device settings are programmable through the
SDA/SCL, serial two-wire interface.
M = 1, 2, 4, 8
N = 32, 40
The phase of one output group relative to the other
can be adjusted through the SDA/SCL interface. For
provided that:
post-divide ratios (P0, P1) that are multiples of 5, the
30MHz < (FIN /M) < 40MHz
total number of phase adjustment steps (n) equals
1200MHz < (FOUT × P) < 1275MHz
the divide-ratio divided by 5. For post-divide ratios
(P0, P1) that are not multiples of 5, the total number
The PLL loop bandwidth is user-selectable by
of steps (n) is the same as the post-divide ratio. The
external filter components or by using the internal
phase adjustment step (
∆Φ) in time units is given as:
loop filter. The PLL loop bandwidth and damping
∆Φ = 1/(n × F
OUT)
factor can be adjusted to meet different system
requirements.
where FOUT is the respective output frequency.
The device operates in a 1.8V supply environment
and is characterized for operation from –40
°C to
+85
°C.
The CDCL6010 is available in a 48-pin QFN (RGZ)
package.
2
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