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SN74LS156N Datasheet(PDF) 2 Page - ON Semiconductor |
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SN74LS156N Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 4 page SN74LS156 http://onsemi.com 111 CONNECTION DIAGRAM DIP (TOP VIEW) Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs A0, A1 Ea, Eb Ea O0 – O3 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES VCC = PIN 16 GND = PIN 8 LOGIC SYMBOL NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 13 3 14 15 EE A0 A0 A1 A1 0 1 23 01 2 3 DECODER a DECODER b 76 5 4 9 10 11 12 14 13 12 11 10 9 12345 6 7 16 15 8 VCC Ea Eb Eb A0 O3b O1b O2b O0b Ea A1 O3a O2a O1a O0a GND |
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