tm

April 2007

©1992 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74VHC240 Rev. 1.3

74VHC240

Octal Buffer/Line Driver with 3-STATE Outputs

Features

General Description

The VHC240 is an advanced high speed CMOS octal

bus buffer fabricated with silicon gate CMOS technology.

It achieves high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The VHC240 is an inverting 3-STATE

buffer having two active-LOW output enables. This

device is designed to drive buslines or buffer memory

address registers.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Descriptions

Order Number

Package

Number

Package Description

74VHC240M

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC240SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC240MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names

Description

3-STATE Output Enable Inputs

Inputs

Outputs 3-STATE Outputs