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AD7764 Datasheet(PDF) 6 Page - Analog Devices |
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AD7764 Datasheet(HTML) 6 Page - Analog Devices |
6 / 32 page AD7764 Rev. 0 | Page 6 of 32 TIMING SPECIFICATIONS AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF+ = 4.096 V, TA = 25°C, CLOAD = 25 pF. Table 3. Parameter Limit at TMIN, TMAX Unit Description fMCLK 500 kHz min Applied master clock frequency 40 MHz max fICLK 250 kHz min Internal modulator clock derived from MCLK 20 MHz max t1 1 × tICLK typ SCO high period t2 1 × tICLK typ SCO low period t3 1 ns typ SCO rising edge to FSO falling edge t4 2 ns typ Data access time, FSO falling edge to data active t5 8 ns max MSB data access time, SDO active to SDO valid t6 40 ns min Data hold time (SDO valid to SCO rising edge) t7 9.5 ns max Data access time (SCO rising edge to SDO valid) t8 2 ns typ SCO rising edge to FSO rising edge t9 32 × tSCO max FSO low period t10 12 ns min Setup time from FSI falling edge to SCO falling edge t11 1 × tSCO min FSI low period t121 32 × tSCO max FSI low period t13 12 ns min SDI setup time for the first data bit t14 12 ns min SDI setup time t15 0 ns max SDI hold time 1 This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained). |
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