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TS75 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

No. de pieza TS75
Descripción Electrónicos  LOW- OLTAGE 2-WIRE DIGITAL TEMPERATURE SENSOR With Thermal Alarm
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Fabricante Electrónico  ETC2 [List of Unclassifed Manufacturers]
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TS75 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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© Andigilog, Inc. 2005
www.andigilog.com
April 2006 - 70A03204
aTS75
Basic Operation
The aTS75 temperature sensing circuitry continuously
produces an analog voltage that is proportional to the
device temperature.
At regular intervals the aTS75
converts the analog voltage to a two’s complement digital
value, which is placed into the temperature register.
The aTS75 has an SMBus compatible digital serial
interface which allows the user to access the data in the
temperature register at any time.
In addition, the serial
interface gives the user easy access to all other aTS75
registers to customize operation of the device.
The aTS75 temperature-to-digital conversion can have 9-,
10-, 11-, or 12-bit resolution as selected by the user,
providing
0.5°C,
0.25°C,
0.125°C,
and
0.0625°C
temperature resolution, respectively.
At power-up the
default conversion resolution is 9-bits.
The conversion
resolution is controlled by the R0 and R1 bits in the
Configuration Register.
Table 1 gives examples of the relationship between the
output digital data and the external temperature. The 9-bit,
10-bit, 11-bit and 12-bit columns in Table 1 indicate the
right-most bit in the output data stream that can contain
temperature information for each conversion accuracy.
Since the output digital data is in two’s-complement format,
the most significant bit of the temperature is the “sign” bit.
If the sign bit is a zero, the temperature is positive and if
the sign bit is a one, the temperature is negative.
The aTS75 has a Shutdown Mode that reduces the
operating current of the aTS75 to 150nA.
This mode is
controlled by the SD bit in the configuration register.
Power Up Default Conditions
The ATS75 always powers up in the following default state:
Thermostat mode: Comparator Mode
O.S. polarity: active low
Fault tolerance: 1 fault (i.e., F0=0 and F1=0 in the
Configuration Register)
TOS = 80°C
THYST = 75°C
Register pointer: 00 (Temperature Register)
Conversion resolution: 9 bits (i.e., R0=0 and R1=0
in the Configuration Register)
After power up these conditions can be reprogrammed via
the serial interface. Refer to the Serial Data Bus Operation
section to for aTS75 programming instructions.
Thermal Alarm Function
The
aTS75
thermal
alarm
function
provides
user
programmable thermostat capability and allows the aTS75
to function as a standalone thermostat without using the
serial interface. The Over-Limit Signal (O.S.) output is the
alarm output. This signal is an open drain output, and at
power-up this pin is configured with active-low polarity.
Table 1. Relationship Between Temperature and Digital
Output
Temperature
Digital Output
Number of bits
used by
conversion
resolution
Always
zero
12-Bit Resolution
0000
11-Bit Resolution
0
0000
10-Bit Resolution
0
0
0000
All Temperatures
9-Bit Resolution
0
0
0
0000
+125°C
0
111
1101
0
0
0
0
0000
+100.0625°C
0
110
0100
0
0
0
1
0000
+50.125°C
0
011
0010
0
0
1
0
0000
+12.25°C
0
000
1100
0
1
0
0
0000
0°C
0
000
0000
0
0
0
0
0000
-20.5°C
1
110
1011
1
0
0
0
0000
-33.25°C
1
101
1110
1
1
0
0
0000
-45.0625°C
1
101
0010
1
1
1
1
0000
-55°C
1
100
1001
0
0
0
0
0000
The O.S. polarity is controlled by the POL bit in the
Configuration Register.
The user-programmable upper
trip-point temperature for the thermal alarm is stored in the
TOS Register, and the user-programmable hysteresis
temperature (i.e., the lower trip point) is stored in the THYST
Register.
The
thermal
alarm
has
two
modes
of
operation:
Comparator Mode and Interrupt Mode.
At power-up the
default is Comparator Mode. The alarm mode is controlled
by the CMP/INTR bit in the Configuration Register.
Fault Tolerance
In either mode the alarm “fault tolerance” setting plays a
role in determining when the O.S. output will be activated.
Fault tolerance refers to the number of consecutive times
an error condition must be detected before the user is
notified. Higher fault tolerance settings can help eliminate
false alarms caused by noise in the system.
The alarm
fault tolerance is controlled by bits F0 and F1 in the
Configuration Register. These bits can be used to set the
fault tolerance to 1, 2, 4 or 6 as shown in Table 4. At
power-up, these bits both default to 0 ( fault tolerance = 1).


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