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TL1593CNS Datasheet(PDF) 4 Page - Texas Instruments |
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TL1593CNS Datasheet(HTML) 4 Page - Texas Instruments |
4 / 19 page TC244A 786- × 488-PIXEL CCD IMAGE SENSOR SOCS056 – JUNE 1996 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 image-sensing and storage areas Figure 1 and Figure 2 show cross sections with potential-well diagrams and top views of image-sensing and storage-area elements. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses to the antiblooming-gate inputs every horizontal-blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. After integration is complete, the signal charge is transferred into the storage area. Twenty-nine full columns and one half-column of elements at the right edge of the image-sensing area are shielded from incident light; these elements provide the dark reference used in subsequent video-processing circuits to restore the video-black level. There are also one full column and one half-column of light-shielded elements at the left edge of the image-sensing area and two lines of light-shielded elements between the image-sensing and image-storage areas. The latter prevent charge leakage from the image-sensing area into the image-storage area. multiplexer with transfer gates and serial registers The color sensitivity of the TC244A is obtained by laminating a color-stripe filter on top of the image-sensing area and aligning it precisely with vertical columns of sensing elements. This separates columns into three groups corresponding to the RGB colors used in the filter. The function of the multiplexer and transfer gates is to transfer the charge line by line from the columns into the corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface region between the serial-register gates and the transfer gates. The multiplexing is activated during the horizontal-blanking interval by applying appropriate pulses to the transfer gates and serial registers. The required pulse timing is shown in Figure 5. A drain has also been included in this area to provide the capability to quickly clear the image-sensing and storage areas of unwanted charge. Such charge can accumulate in the imager during the start-up of operation or under special circumstances when nonstandard TV operation is desired. correlated-clamp sample-and-hold amplifier with charge-detection nodes Figure 6 illustrates the correlated-clamp sample-and-hold amplifier circuit. Charge is converted into a video signal by transferring the charge onto a floating-diffusion structure in detection node1 that is connected to the gate of MOS transistor Q1. The proportional charge-induced signal is then processed by the circuit shown in Figure 6. This circuit consists of a low-pass filter formed by Q1 and C2, coupling-capacitor C1, dummy-detection node 2, which restores the dc bias on the gate of Q3, sampling transistor Q5, holding-capacitor C3, and output-buffer Q6. Transistors Q2, Q4, and Q7 are current sources for each corresponding stage of the amplifier. The parameters of this high-performance signal-processing amplifier have been optimized to minimize noise and maximize the video signal. The signal processing begins with a reset of detection node 1 and restoration of the dc bias on the gate of Q3 through the clamping function of dummy-detection node 2. After the clamping is completed, the new charge packet is transferred onto detection node 1. The resulting signal is sampled by the sampling-transistor Q5 and is stored on the holding-capacitor C3. This process is repeated periodically and is correlated to the charge transfer in the registers. The correlation is achieved automatically since the same clock lines used in registers φ-S2 and φ-S3 for charge transport serve for reset and sample. The multiple use of the clock lines significantly reduces the number of signals required to operate the sensor. The amplifier also contains an internal voltage-reference generator that provides the reference bias for the reset and clamp transistors. The detection nodes and the corresponding amplifiers are located some distance from the edge of the storage area; therefore, eleven dummy elements are incorporated at the end of each serial register to span the distance. The location of the dummy elements, which are considered to be part of the amplifiers, is shown in the functional block diagram. |
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