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TDA10021 Datasheet(PDF) 6 Page - NXP Semiconductors

No. de pieza TDA10021
Descripción Electrónicos  DVB-C channel receiver
Download  16 Pages
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Fabricante Electrónico  PHILIPS [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA10021 Datasheet(HTML) 6 Page - NXP Semiconductors

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2001 Oct 01
6
Philips Semiconductors
Product specification
DVB-C channel receiver
TDA10021HT
Note
1. All inputs (I) are TTL, 5 V tolerant (except pins XIN, VIP and VIM). OD are open-drain outputs, so they must be
connected by a pull-up resistor to either VDDD33 or VDDD50.
DO[7:4]
37 to 40
O
data output bus: this 8-bit parallel data is the output from the TDA10021HT after
demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected (parameter SERINT = 0, index 20) then
DO[7:0] is the transport stream output. When the serial interface is selected
(parameter SERINT = 1, index 20) then the serial output is on pin DO[0].
VDDDI8
41
S
digital supply voltage for the core (1.8 V typ.)
VSSD18
42
G
digital ground for the core
VDDD33
43
S
digital supply voltage for the pads (3.3 V typ.)
VSSD33
44
G
digital ground for the pads
DO[3:0]
45 to 48
O
data output bus: this 8-bit parallel data is the output from the TDA10021HT after
demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected then DO[7:0] is the transport stream
output. When the serial interface is selected then the serial output is on pin DO[0].
VSSD1
49
G
ground return for the digital switching circuitry (ADC)
VDDD1
50
S
power supply input for the digital switching circuitry 1.8 V (ADC)
VSSA2
51
G
ground return for the analog clock drivers (ADC)
VDDA2
52
S
power supply input for the analog clock drivers 3.3 V (ADC)
Vref(pos)
53
O
this is a positive voltage reference for the ADC. It is derived from the internal band
gap voltage, VBG, with an on-chip fully differential amplifier.
Vref(neg)
54
O
this is the negative voltage reference for the ADC. It is derived from the internal
band gap voltage, VBG, with an on-chip fully differential amplifier.
VDDA3
55
S
power supply input for the analog circuits 3.3 V (ADC)
VSSA3
56
G
ground return for analog circuits (ADC)
VIM
57
I
negative input to the ADC: this pin is DC biased to half-supply through an internal
resistor divider (2
× 20 kΩ resistors). In order to stay in the range of the ADC,
VIP − VIM should remain between the input range corresponding to the SW
register (index 1B
− default value = 0.5 V).
VIP
58
I
positive input to the ADC: this pin is DC biased to half-supply through an internal
resistor divider (2
× 20 kΩ resistors). In order to stay in the range of the ADC,
VIP − VIM should remain between the input range corresponding to the SW
register (index 1B
− default value = 0.5 V).
VSSA3
59
G
ground return for analog circuits (ADC)
VDDA3
60
S
power supply input for the analog circuits 3.3 V (ADC)
VCCD(PLL)
61
S
power supply for the PLL digital section 1.8 V
DGND
62
G
ground connection for the PLL digital section
PLLGND
63
G
ground connection for the PLL analog section
VCCA(PLL)
64
S
power supply for the PLL analog section 3.3 V
SYMBOL
PIN
TYPE(1)
DESCRIPTION


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