 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TDA5149 Datasheet(PDF) 9 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
TDA5149 Datasheet(HTML) 9 Page - NXP Semiconductors |
|
|
9 / 28 page  1996 May 06 9 Philips Semiconductors Product specification 12 V Voice Coil Motor (VCM) driver and spindle motor pre-driver combination chip TDA5149G Power-on/power-off reset The power-on reset circuitry monitors the analog, digital and general supplies. The voltage thresholds have been set internally for both supplies, i.e. 4.4 V for VDDA and VDDD, and 10.5 V for VDD. External adjustment and filtering, to suppress supply spikes, has been made possible through the pins POR5ADJ and POR12ADJ. When either of the supplies falls below their threshold levels, the reset circuit provides two active LOW output signals. The RESETA signal is a full CMOS output and the RESETP signal has an active pull-down MOS transistor with a passive pull-up resistance of 10 k Ω. The latter can be used for emulation purposes. Both signals remain LOW until the supply voltages are again above the threshold level, delayed by a time constant period that is determined by the value of the capacitor connected to pin PORDELAY. A park sequence is initiated on a reset fault. This includes disabling the actuator latch drivers and starting a delayed spindle brake operation by switching on the low side pre-drivers simultaneously. This brake delay is determined by an external RC combination connected to BRAKEDELAY. Actuator PARK and spindle BRAKE can also be controlled via the serial port. At power-up, the two reset output signals (RESETA and RESETP) will remain LOW as long as either supply voltage is below the specified threshold plus the hysteresis voltage. Once the supply voltages are above their specific trip levels, the two reset signals become HIGH after the power-on reset delay (PORDELAY). This delay time is determined by the value of the capacitor connected to the PORDELAY pin. Powerless park/brake As with the normal retract procedure, an actuator park sequence is initiated whenever a power-down situation occurs. The power-on/power-off reset circuit generates the two active LOW reset signals and also activates the VCM park circuit. The VCM park circuit provides a voltage, retrieved from the rectified back EMF voltage of the running-out spindle, of 1.2 V (typ.) to the VCM pin. The voltage at pin VCM+ is 0 V. This voltage is supplied by the capacitor CCLAMP that is connected to the CLAMP pin. This capacitor smooths the rectified back EMF and stores the electrical energy generated by the motor. To ensure that the stored energy in the clamp capacitor is only used for the park operation, the CLAMP input must be isolated from the power supply. This can be achieved by using a Schottky diode or a reverse connected N-channel power FET (see Fig.1). The TDA5149G provides an output H0 to control this power FET. At power-down the brake delay circuit is also enabled. The brake delay circuit is supplied by the energy stored in the capacitor (charged during normal operation from VDD) that is connected to the BRAKEPOWER pin. Both the BRAKEDELAY and BRAKEPOWER pins are then isolated from the 12 V supply voltage. When the voltage on the BRAKEDELAY pin reaches a value of 1.6 V (typ.), the low-side external power FETs are turned on to brake the spindle motor. The BRAKEPOWER capacitor then supplies the current to keep the power FETs conducting. This means that the voltage on this capacitor decreases with time. Serial port The serial port is used to modify the various operational modes of the TDA5149G and to adjust the timing parameters to ensure the proper commutation sequence of the spindle motor. It is a synchronous, slave only, three-wire communication port with data (SDATA), clock (SCLOCK) and enable (SENABLE) inputs. The serial port requires the data to be sent in bytes, the LSB (data 0) to be sent first and the MSB (address 2) last. The three most significant bits (MSBs) determine the register address, the remaining five bits represent the data, which means up to 8 registers can be independently addressed. When SENABLE is LOW, the serial port is disabled and the IC is not affected by any change both on SDATA and SCLOCK. When SENABLE is HIGH the data is written serially to the shift register on the rising edge of SCLOCK. When SENABLE goes LOW the shifting sequence is stopped and the last 8 bits that are clocked in are latched into the appropriate control register. Therefore, the transmission of two consecutive bytes requires that SENABLE is LOW for at least a duration of ‘t’ (see Chapter “Characteristics”). |
Número de pieza similar - TDA5149 |
|
Descripción similar - TDA5149 |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
