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LM2506GR Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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LM2506GR Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 19 page  Functional Description (Continued) uses two bits that are already required in the 6-MC cycle transaction. Since double-edge clocking is used with two data signals, adding one clock cycle to the transaction actu- ally adds four bits. One of these bits is absolutely required - data enable - thus the others are allocated to Parity and the frame sequence (F[1:0]). Therefore total overhead for each pixel is 3/24 or 12.5% in 18-bit RGB mode. HOST SIDE FUNCTION The LM2506 in serializer mode simply increments the two bit field F[1:0] on every pixel or frame transmitted. Therefore every four frames, the pattern will repeat. It is very unlikely that this pattern would be found within the payload data, and if it were found, the probability that it would repeat for many frames becomes infinitely small. DISPLAY SIDE FUNCTION The LM2506 in deserializer mode, upon a normal power up sequence, starts in the proper synchronization. It looks for the incrementing pattern for N (N=4or8) pixels (frames) and finding it, starts to output the pixel gray scale data and timing signals. If a random bit error occurs in the F[1:0] field, the hysteresis counter decrements by one, but the chip continues to output data normally. The next frame will likely recover, increment- ing the hysteresis counter back to the maximum and things will continue normally. Likewise if a random bit error occurs in the gray scale data, it only effects that bit and transmission will continue normally on the next frame (pixel). The worst case data bit error would cause a one pixel wide glitch in the HS, VS or DE signals. This would likely cause a visible jump in the display, but it would recover in a maximum of one display frame time. (typically under 20mS) If however, a clock slip or error occurs, the next N frames will be bad and the F[1:0] field will not be detected properly for each frame after the clock error. In this case, the hysteresis counter will decrement to zero quickly (again where N=4 or 8 pixels). This action shuts down the output data (output PCLK held Low), and initiates a search function for the increment- ing sequence. Detecting the Incrementing Sequence Acquiring synchronization from a random position requires looking only at the MD1 line, as this line contains the incre- menting sequence F[1:0]. This is done by examining six two-bit pairs and comparing each pair to an incrementing sequence. A snapshot of the data is first taken and loaded into six two-bit adders. The adders increment by one and then compare the same bit positions in the next 12-bits. If a match is found a flag is set for that bit pair. This same procedure is followed until there is only one flag set. After only one flag is set, the synchronization is tested for the full count of the hysteresis counter (4 or 8 pixels) and then a valid synchronization is declared and pixel data and strobes are again output to the display. In the best case, this parallel method of detecting sync is very fast. If only one flag exists on the first frame tested, then resynchronization can occur in as little as 6 pixel times (assuming NNE = no new errors). If however, random data emulates an incrementing sequence for several pixels of time, the process can take longer. It is data dependant. It is important to note that a pathological case exists, as it does for most pattern detection methods, where the data can forever emulate this incrementing sequence, when in fact the true F[1:0] is not detected. This F’[1:0] (F prime) may occur for several pixels, but becomes linearly less probable as more and more data passes through the system. 20125526 FIGURE 11. Serializer Mode Input Timing for RGB Interface www.national.com 10 |
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