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TC7126 Datasheet(PDF) 10 Page - Microchip Technology |
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TC7126 Datasheet(HTML) 10 Page - Microchip Technology |
10 / 26 page TC7126/A DS21458C-page 10 © 2006 Microchip Technology Inc. 4.0 ANALOG SECTION In addition to the basic integrate and de-integrate dual slope cycles discussed above, the TC7126A design incorporates an auto-zero cycle. This cycle removes buffer amplifier, integrator and comparator offset volt- age error terms from the conversion. A true digital zero reading results without external adjusting potentiome- ters. A complete conversion consists of three phases: 1. Auto-Zero phase 2. Signal Integrate phase 3. Reference Integrate phase 4.1 Auto-Zero Phase During the auto-zero phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits com- parator offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages. The auto-zero phase residual is typically 10 μV to 15μV. The auto-zero cycle length is 1000 to 3000 clock periods. 4.2 Signal Integrate Phase The auto-zero loop is entered and the internal differen- tial inputs connect to VIN+ and VIN-. The differential input signal is integrated for a fixed time period. The TC7126/A signal integration period is 1000 clock periods or counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time period is: EQUATION 4-1: The differential input voltage must be within the device Common mode range when the converter and mea- sured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, VIN- should be tied to analog common. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. 4.3 Reference Integrate Phase The third phase is reference integrate or de-integrate. VIN- is internally connected to analog common and VIN+ is connected across the previously charged refer- ence capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is propor- tional to the input signal and is between 0 and 2000 counts. The digital reading displayed is: EQUATION 4-2: TSI = 4 FOSC x 1000 Where: FOSC = external clock frequency. VIN VREF 1000 |
Número de pieza similar - TC7126_06 |
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Descripción similar - TC7126_06 |
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