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4

spikes will invariably be found

at the I SENSE pins. The noise

spikes could trip the current limit

threshold which is only 100 mV.

R

adjusted so as to reduce the

switching noise well below 100

mV to prevent false current limit-

ing. The sum of

the DC level plus

the noise peak

will determine

the current limit-

ing value. As in

most switching

circuits it may be difficult to determine the true noise amplitude

without careful attention to grounding of the oscilloscope probe.

Use the shortest possible ground lead for the probe and con-

nect exactly at the GND terminal of the amplifier. Suggested

starting values are C

The required value of R

culated by:

R

where R

maximum desired current. In current mode the required value

of each R

divided down by 2 (see Figure B). If R

divide down the sense voltage. The shutdown divider network

will also have an effect on the filtering circuit.

BYPASSING

Adequate bypassing of the power supplies is required for

proper operation. Failure to do so can cause erratic and low

efficiency operation as well as excessive ringing at the out-

puts. The Vs supply should be bypassed with at least a 1µF

ceramic capacitor in parallel with another low ESR capacitor

of at least 10µF per amp of output current. Capacitor types

rated for switching applications are the only types that should

be considered. The bypass capacitors must be physically

connected directly to the power supply pins. Even one inch of

lead length will cause excessive ringing at the outputs. This is

due to the very fast switching times and the inductance of the

lead connection. The bypassing requirements of the Vcc supply

are less stringent, but still necessary. A .1µF to .47µF ceramic

capacitor connected directly to the Vcc pin will suffice.

STARTUP CONDITIONS

The high side of the all N channel output bridge circuit is

driven by bootstrap circuit and charge pump arrangement. In

order for the circuit to produce a 100% duty cycle indefinitely

the low side of each half bridge circuit must have previously

been in the ON condition. This means, in turn, that if the input

signal to the SA03 at startup is demanding a 100% duty cycle,

the output may not follow the command and may be in a tri-

state condition. The ramp signal must cross the input signal

at some point to correctly determine the output state. After

the ramp crosses the input signal level one time, the output

state will be correct thereafter.

OPERATING

CONSIDERATIONS

SA03

GENERAL

Please read Application Note 30 on "PWM Basics". Refer

to Application Note 1 "General Operating Considerations" for

helpful information regarding power supplies, heat sinking and

mounting. Visit www.apexmicrotech.com for design tools that

help automate pwm filter design; heat sink selection; Apex’s

complete Application Notes library; Technical Seminar Work-

book; and Evaluation Kits.

CLOCK CIRCUIT AND RAMP GENERATOR

The clock frequency is internally set to a frequency of ap-

proximately 45kHz. The CLK OUT pin will normally be tied to

the CLK IN pin. The clock is divided by two and applied to an

RC network which produces a ramp signal at the –PWM/RAMP

pin. An external clock signal can be applied to the CLK IN pin

for synchronization purposes. If a clock frequency lower than

45kHz is chosen an external capacitor must be tied to the

–PWM/RAMP pin. This capacitor, which parallels an internal

capacitor, must be selected so that the ramp oscillates 4 volts

p-p with the lower peak 3 volts above ground.

PWM INPUTS

The full bridge driver may be accessed via the pwm input

comparator. When +PWM > -PWM then A OUT > B OUT. A

motion control processor which generates the pwm signal can

drive these pins with signals referenced to GND.

PROTECTION CIRCUITS

In addition to the externally programmable current limit there

is also a fixed internal current limit which senses only the high

side current. It is nominally set to 140% of the continuous

rated output current. Should either of the outputs be shorted

to ground the high side current limit will latch off the output

transistors. Also, the temperature of the output transistors is

continually monitored. Should a fault condition occur which

raises the temperature of the output transistors to 165°C

the thermal protection circuit will activate and also latch off

the output transistors. In either case, it will be necessary to

remove the fault condition and recycle power to V

the circuit.

CURRENT LIMIT

There are two load current sensing pins, I SENSE A and I

SENSE B. The two pins can be shorted in the voltage mode

connection but both must be used in the current mode con-

nection (see figures A and B). It is recommended that R

LIMIT

resistors be non-inductive. Load current flows in the I SENSE

pins. To avoid errors

due to lead lengths

connect the I LIMIT/

SHDN pin directly to

the R

(through the filter net-

work and shutdown

divider resistor) and

connect the R

LIMIT

resistors directly to

the GND pin.

Switching noise

This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.

SA03U REV G OCTOBER 2006 © 2006 Apex Microtechnology Corp.