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FCE467

SERIAL

INTERFACE

OR

3-WIRE

(H level)

REGULATOR

PLL

PWDWN

CP

CZ

CKREF

COAST

INV

CKEXT

CKREFO

CKAO

CKBO

CKADCO

B0 to B7

BOR

R0 to R7

OE

G0 to G7

BBOT

BCLP

RBOT

RCLP

GBOT

GCLP

DEC2

DEC1

HSYNC

n.c.

HSYNCI

ADD2

BIN

BGAINC

BAGC

GAGC

Vref

RDEC

RIN

RGAINC

RAGC

GDEC

GIN

GGAINC

BDEC

ADD1

SEN

SCL

SDA

DIS

BLUE CHANNEL

GREEN CHANNEL

TDA8752B

RED CHANNEL

ADC

GOR

ROR

MUX

CLAMP

OUTPUTS

6

VCCAR

11

VCCAG

19

VCCAB

27

VDDD

40

AGNDG

21

VCCOG

69

VCCOB

59

VCCOR

79

VCCD

95

VCCA(PLL)

99

VCCO(PLL)

85

CLP

89

AGNDR

13

VSSD

41

AGNDB

29

OGNDG

60

OGNDR

70

AGNDPLL

96

OGNDB

48

DGND

86

OGNDPLL

82

12

10

3

22

24

28

26

20

18

14

16

33

34

38

TDO

TCK

35

36

42

39

37

90

1, 5, 30, 31, 43 , 44

50, 51, 100

4

2

88

97

98

32

8

9

7

71 to 78

45

17

15

61 to 68

87

46

25

23

49, 52 to 58

47

93

94

92

80

91

84

83

81

Fig.1 Block diagram.