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STK10C68-5PF35I Datasheet(PDF) 4 Page - Simtek Corporation |
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STK10C68-5PF35I Datasheet(HTML) 4 Page - Simtek Corporation |
4 / 12 page STK10C68 March 2006 4 Document Control # ML0006 rev 0.2 SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%) Note i: If W is low when E goes low, the outputs remain in the high-impedance state. Note j: E or W must be ≥ VIH during address transitions. NE ≥ VIH. SRAM WRITE CYCLE #1: W Controlledj SRAM WRITE CYCLE #2: E Controlledj NO. SYMBOLS PARAMETER STK10C68-25 STK10C68-35 STK10C68-45 STK10C68-55 UNITS #1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 30 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 0 ns 20 tWLQZ h, i tWZ Write Enable to Output Disable 10 13 14 15 ns 21 tWHQX tOW Output Active after End of Write 5 5 5 5 ns PREVIOUS DATA DATA OUT E ADDRESS 12 tAVAV W 16 tWHDX DATA IN 19 tWHAX 13 tWLWH 18 tAVWL 17 tAVWH DATA VALID 20 tWLQZ 15 tDVWH HIGH IMPEDANCE 21 tWHQX 14 tELWH DATA OUT E ADDRESS 12 tAVAV W DATA IN 13 tWLEH 17 tAVEH DATA VALID HIGH IMPEDANCE 14 tELEH 18 tAVEL 19 tEHAX 15 tDVEH 16 tEHDX |
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