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CS5571-ISZ Datasheet(PDF) 6 Page - Cirrus Logic |
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CS5571-ISZ Datasheet(HTML) 6 Page - Cirrus Logic |
6 / 32 page CS5571 6 DS768A5 6/25/07 14:12 SWITCHING CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. 9. Reset must not be released until the power supplies and the voltage reference are within specification. 10. CAL must remain high until RDY falls at the end of the calibration time. 11. CAL can be controlled by the same signal used for RST. If CAL goes high simultaneously with RST, a calibration will be performed. CAL must remain high until RDY falls. 12. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls. 13. If CONV is held low continuously, conversions occur every 160 MCLK cycles. If RDY is tied to CONV, conversions will occur every 162 MCLKs. If CONV is operated asynchronously to MCLK, a conversion may take up to 164 MCLKs. RDY falls at the end of conversion. Parameter Symbol Min Typ Max Unit Master Clock Frequency Internal Oscillator External Clock XIN fclk 12 0.5 14 16 16 16.2 MHz MHz Master Clock Duty Cycle 40 - 60 % Reset RST Low Time (Note 9) tres 1- - µs RST rising to RDY falling Internal Oscillator External Clock twup - - 120 1536 - - µs MCLKs Calibration CAL pulse width (Note 10, 11) tpw 4- - MCLKs CAL high setup time to RST rising (Note 10, 11) tccw 0- - ns Calibration Time RST rising (CAL high) to RDY falling tscl - 167298 - MCLKs Calibration Time CAL rising (RST high) to RDY falling tcal - 167298 - MCLKs Conversion CONV Pulse Width tcpw 4- - MCLKs BP/UP setup to CONV falling (Note 12) tscn 0- - ns CONV low to start of conversion tscn -- 2 MCLKs Perform Single Conversion (CONV high before RDY falling) tbus 20 - - MCLKs Conversion Time (Note 13) Start of Conversion to RDY falling tbuh -- 164 MCLKs |
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