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CS5560-ISZ Datasheet(PDF) 7 Page - Cirrus Logic |
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CS5560-ISZ Datasheet(HTML) 7 Page - Cirrus Logic |
7 / 32 page CS5560 DS713A5 7 7/31/07 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. 12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resister. 13. SCLK = MCLK/2. Parameter Symbol Min Typ Max Unit Serial Port Timing in SSC Mode (SMODE = VL) RDY falling to MSB stable t1 --2 - MCLKs Data hold time after SCLK rising t2 -10 - ns Serial Clock (Out) Pulse Width (low) (Note 12, 13) Pulse Width (high) t3 t4 50 50 - - - - ns ns RDY rising after last SCLK rising t5 -8 - MCLKs MCLK RDY SCLK(o) SDO MSB MSB–1 LSB LSB+1 CS t1 t2 t3 t4 t5 Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale) |
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