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LB11691H Datasheet(PDF) 5 Page - Sanyo Semicon Device |
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LB11691H Datasheet(HTML) 5 Page - Sanyo Semicon Device |
5 / 21 page LB11691H No.8314-5/21 Three-phase logic truth table (1)120 ° (HSEL = “L”) F/R = “L” F/R = “H” IN1 IN2 IN3 IN1 IN2 IN3 Upper side gate Lower side gate HP 1 H L H L H L VH UL H 2 H L L L H H WH UL L 3 H H L L L H WH VL H 4 L H L H L H UH VL L 5 L H H H L L UH WL H 6 L L H H H L VH WL L (2)60 ° (HSEL = “H”) F/R = “L” F/R = “H” IN1 IN2 IN3 IN1 IN2 IN3 Upper side gate Lower side gate HP 1 H H H L L L VH UL H 2 L H H H L L WH UL L 3 L L H H H L WH VL H 4 L L L H H H UH VL L 5 H L L L H H UH WL H 6 H H L L L H VH WL L • The condition with the upper gate = VH and the lower gate = UL corresponds to a state in which the upper FET is turned ON when the VH pin is connected and the lower FET is turned ON when the UL pin is connected. • The HP output is an open collector output. Therefore, “H” level corresponds to an open state. Pin Assignment 19 RC 20 CSD 21 FAIL 22 HP 23 CP2 24 CP1 25 LVS 26 V5 27 V12 28 VCC 29 VB 30 GND 31 RFGND 32 RF 33 (NC) 34 WL 35 WOUT 36 WH 18 FV 17 PWM 16 TOC 15 EI- 14 EI+ 13 (NC) 12 F/R 11 HSEL 10 RES Top view 9 IN3 8 IN2 7 IN1 6 UH 5 UOUT 4 UL 3 VH 2 VOUT 1 VL LB11691H |
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