Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
SI5368C-B-GQ Datasheet(PDF) 9 Page - Silicon Laboratories |
|
SI5368C-B-GQ Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 18 page Si5368 Preliminary Rev. 0.3 9 13 57 CS0_C3A CS1_C4A I/O LVCMOS Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator. If manual clock selection is chosen, and if CKSEL_PIN =1, the CKSEL pins control clock selection and the CKSEL_REG bits are ignored. If CKSEL_PIN =0, the CKSEL_REG register bits control this function and these inputs tristate. If these pins are not function- ing as the CS[1:0] inputs and auto clock selection is enabled, then they serve as the CKIN_n active clock indicator. 0 = CKIN3 (CKIN4) is not the active input clock 1 = CKIN3 (CKIN4) is currently the active input to the PLL The CKn_ACTV_REG bit always reflects the active clock status for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be reflected on the CnA pin with active polarity controlled by the CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates. This pin has a weak pull-down. 16 17 XA XB IANALOG External Crystal or Reference Clock. External crystal should be connected to these pins to use exter- nal oscillator based reference. If a single-ended external refer- ence is used, ac couple reference clock to XA input and leave XB pin floating. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pins. 21 FS_ALIGN I LVCMOS FSYNC Alignment Control. If FSYNC_ALIGN_PIN = 1 and CK_CONFIG = 1, a logic high on this pin causes the FS_OUT phase to be realigned to the ris- ing edge of the currently active input sync (CKIN_3 or CKIN_4). If FSYNC_ALIGN_PIN = 0, this pin is ignored and the FSYNC_ALIGN_REG bit performs this function. 0 = No realignment. 1 = Realign. This pin has a weak pull-down. 29 30 CKIN4+ CKIN4– IMULTI Clock Input 4. Differential clock input. This input can also be driven with a sin- gle-ended signal. CKIN4 serves as the frame sync input associ- ated with the CKIN2 clock when CK_CONFIG_REG =1. Table 3. Si5368 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. CS[1:0] Active Input Clock 00 CKIN1 01 CKIN2 10 CKIN3 11 CKIN4 |
Número de pieza similar - SI5368C-B-GQ |
|
Descripción similar - SI5368C-B-GQ |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |