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SN74AS30DR Datasheet(PDF) 5 Page - Texas Instruments |
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SN74AS30DR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 19 page SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES tPLZ tPHL tPLH 0.3 V tPZL tPLH tPHL LOAD CIRCUIT FOR 3-STATE OUTPUTS From Output Under Test Test Point S1 CL = 50 pF (see Note A) 7 V 3 V 3 V 0 V 0 V th tsu VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Timing Input Data Input 3 V 3 V 0 V 0 V High-Level Pulse Low-Level Pulse tw VOLTAGE WAVEFORMS PULSE DURATIONS Input Out-of-Phase Output (see Note C) 3 V 3 V 0 V 0 V VOL VOH VOH VOL Output Control (low-level enabling) Waveform 1 S1 Closed (see Note B) Waveform 2 S1 Open (see Note B) ≈0 V VOH VOL ≈3 V In-Phase Output 0.3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS VCC Test Point From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS From Output Under Test Test Point CL = 50 pF (see Note A) 500 Ω 500 Ω 500 Ω 500 Ω 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V tPHZ tPZH 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms |
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