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AD9245BCPZRL7-652 Datasheet(PDF) 4 Page - Analog Devices |
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AD9245BCPZRL7-652 Datasheet(HTML) 4 Page - Analog Devices |
4 / 32 page AD9245 Rev. D | Page 4 of 32 AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted. Table 2. AD9245BCP-80 Parameter Min Typ Max Unit RESOLUTION 14 Bits ACCURACY No Missing Codes Guaranteed Offset Error1 ±0.30 ±1.2 % FSR Gain Error ±0.28 % FSR Gain Error1 ±0.70 ±4.16 % FSR Differential Nonlinearity (DNL)2 ±0.5 ±1.0 LSB Integral Nonlinearity (INL)2 ±1.4 ±5.15 LSB TEMPERATURE DRIFT Offset Error1 ±10 ppm/°C Gain Error ±12 ppm/°C Gain Error1 ±17 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) ±3 ±34 mV Load Regulation @ 1.0 mA ±2 mV Output Voltage Error (0.5 V Mode) ±6 mV Load Regulation @ 0.5 mA ±1 mV INPUT REFERRED NOISE VREF = 0.5 V 1.86 LSB rms VREF = 1.0 V 1.17 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V 1 V p-p Input Span, VREF = 1.0 V 2 V p-p Input Capacitance3 7 pF REFERENCE INPUT RESISTANCE 7 kΩ POWER SUPPLIES Supply Voltage AVDD 2.7 3.0 3.6 V DRVDD 2.25 2.5 3.6 V Supply Current IAVDD2 122 138 mA IDRVDD2 9 mA PSRR ±0.01 % FSR POWER CONSUMPTION Low Frequency Input4 366 mW Standby Power5 1.0 mW 1 With a 1.0 V internal reference. 2 Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure. 4 Measured at ac specification conditions without output drivers. 5 Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND). |
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