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TP2635 Datasheet(PDF) 1 Page - Supertex, Inc

No. de pieza TP2635
Descripción Electrónicos  P- Channel Enhancement-Mode Vertical DMOS FETs
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Fabricante Electrónico  SUTEX [Supertex, Inc]
Página de inicio  http://www.supertex.com
Logo SUTEX - Supertex, Inc

TP2635 Datasheet(HTML) 1 Page - Supertex, Inc

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1
TP2635/TP2640
Features
Low threshold — -2.0V max.
High input impedance
Low input capacitance
Fast switching speeds
Low on resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
These low threshold enhancement-mode (normally-off)
transistors utilize a vertical DMOS structure and Supertex’s
well-proven silicon-gate manufacturing process. This
combination produces devices with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally
induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Device
Package Options
BV
DSS/BVDGS
R
DS(ON) (max)
V
GS(th) (max)
I
D(ON) (min)
SO-8
TO-92
TP2635
-
TP2635N3
-350V
15Ω
-2.0V
-0.7A
-
TP2635N3-G
TP2640
TP2640LG
TP2640N3
-400V
15Ω
-2.0V
-0.7A
TP2640LG-G
TP2640N3-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
Value
Drain to source voltage
BV
DSS
Drain to gate voltage
BV
DGS
Gate to source voltage
±20V
Operating and storage temperature
-55°C to +150°C
Soldering temperature1
+300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Note 1. Distance of 1.6mm from case for 10 seconds.
Pin Configurations
S G D
TO-92
1
2
3
4
8
7
6
5
SO-8
(top view)
NC
NC
S
G
D
D
D
D
P- Channel Enhancement-Mode
Vertical DMOS FETs


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