TLC5615IDGKR datasheet(4/21 Pages) TI

No. de pieza	TLC5615IDGKR

Descripción Electrónicos	10-BIT DIGITAL-TO-ANALOG CONVERTERS

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Fabricante Electrónico	TI [Texas Instruments]

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VOLTAGE OUTPUT (OUT)

DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1)

OUTPUT SWITCHING CHARACTERISTICS

TLC5615C, TLC5615I

SLAS142E – OCTOBER 1996 – REVISED JUNE 2007

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VO

Voltage output range

RL= 10kΩ

0

VDD–0.4

V

Output load regulation accuracy

VO(OUT) = 2V,

RL = 2kΩ

0.5

LSB

IOSC

Output short circuit current

OUT to VDD or AGND

20

mA

VOL(low)

Output voltage, low-level

IO(OUT)≤ 5mA

0.25

V

VOH(high)

Output voltage, high-level

IO(OUT)≤– 5mA

4.75

V

REFERENCE INPUT (REFIN)

VI

Input voltage

0

VDD–2

V

ri

Input resistance

10

M

Ω

Ci

Input capacitance

5

pF

DIGITAL INPUTS (DIN, SCLK, CS)

VIH

High-level digital input voltage

2.4

V

VIL

Low-level digital input voltage

0.8

V

IIH

High-level digital input current

VI = VDD

±1

µA

IIL

Low-level digital input current

VI = 0

±1

µA

Ci

Input capacitance

8

pF

DIGITAL OUTPUT (DOUT)

VOH

Output voltage, high-level

IO = –2mA

VDD–1

V

VOL

Output voltage, low-level

IO = 2mA

0.4

V

POWER SUPPLY

VDD

Supply voltage

4.5

5

5.5

V

VDD = 5.5V, No load,

Vref = 0

150

250

µA

All inputs = 0V or VDD

IDD

Power supply current

VDD= 5.5V, No load,

Vref = 2.048V

230

350

µA

All inputs = 0V or VDD

ANALOG OUTPUT DYNAMIC PERFORMANCE

Vref = 1VPP at 1kHz + 2.048Vdc,

Signal-to-noise + distortion, S/(N+D)

60

dB

code = 11 1111 1111(1)

(1)

The limiting frequency value at 1VPP is determined by the output-amplifier slew rate.

PARAMETER

MIN

NOM

MAX

UNIT

tsu(DS)

Setup time, DIN before SCLK high

45

ns

th(DH)

Hold time, DIN valid after SCLK high

0

ns

tsu(CSS)

Setup time, CS low to SCLK high

1

ns

tsu(CS1)

Setup time, CS high to SCLK high

50

ns

th(CSH0)

Hold time, SCLK low to CS low

1

ns

th(CSH1)

Hold time, SCLK low to CS high

0

ns

tw(CS)

Pulse duration, minimum chip select pulse width high

20

ns

tw(CL)

Pulse duration, SCLK low

25

ns

tw(CH)

Pulse duration, SCLK high

25

ns

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

tpd(DOUT)

Propagation delay time, DOUT

CL = 50pF

50

ns

4

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