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ML145404RP Datasheet(PDF) 6 Page - LANSDALE Semiconductor Inc.

No. de pieza ML145404RP
Descripción Electrónicos  Drivers/Receivers RS 232/EIA-232-E and CCITT V.28
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Fabricante Electrónico  LANSDALE [LANSDALE Semiconductor Inc.]
Página de inicio  http://www.lansdale.com
Logo LANSDALE - LANSDALE Semiconductor Inc.

ML145404RP Datasheet(HTML) 6 Page - LANSDALE Semiconductor Inc.

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Page 6 of 8
Issue A
LANSDALE Semiconductor, Inc.
ML145403, ML145404, ML145405, ML145408
DI1 – DIn
Data Input Pins
These are the high impedance digital input pins to the driv-
ers. Input voltage levels on these pins are LSTTL compatible
and must be between VCC and GND. A weak pull–up on each
input sets all unused DI pins to VCC, causing the correspon-
ding unused driver outputs to be at VSS.
Tx1 – TXn
Transmit Data Output Pins
These are the EIA–232–E transmit signal output pins, which
swing from VDD to VSS. A logic 1 at the DI input causes the
corresponding Tx output to swing to VSS. A logic 0 at the DI
input causes the corresponding Tx out to swing to VDD. The
actual levels and slew rate achieved will depend on the output
loading (RL//CL).
LEGACY APPLICATION INFORMATION
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive de-
vice current.
The diode D1 prevents excessive current from flowing
through an internal diode from the VCC pin to the VDD pin-
when VDD < VCC by approximately 0.6 V or greater. This
high current condition can exist for a short period of time dur-
ing power up/down. Additionally, if the + 12 V supply is
switched off while the + 5 V is on and the off supply is a low
impedance to ground, the diode D1 will prevent current flow
through the internal diode.
The diode D2 is used as a voltage clamp, to prevent VSS
from drifting positive to VCC, in the event that power is re-
moved from VSS (Pin 12). If VSS power is removed, and the
impedance from the VSS pin to ground is greater than approxi-
mately 3 k
Ω, this pin will be pulled to VCC by internal circuit-
ry causing excessive current in the VCC pin.
If by design, neither of the above conditions are allowed to
exist, then the diodes D1 and D2 are not required.
ESD PROTECTION – CAUTION
ESD protection on IC devices that have their pins accessible
to the outside world is essential. High static voltages applied to
the pins when someone touches them either directly or in
directly can cause damage to gate oxides and transistor junc-
tions by coupling a portion of the energy from the I/O pin to
the power supply buses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 4 shows a technique
which will clamp the ESD voltage at approximately ± 15 V
using the MMBZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
capacitors C1 – C3. This scheme has provided protection to the
interface part up to ± 10kV, using the human body model test.
R
R
R
R
R
VDD
Rx1
Tx1
Rx2
Tx2
Rx3
Tx3
Rx4
Tx4
Rx5
1
2
3
4
5
6
7
8
9
10
DI1
DO2
DI2
DO3
DI3
DO4
DI4
DO5
DI5
GND
22
21
20
19
18
17
16
15
14
13
24
23
11
12
VCC
DO1
VSS
Tx5
+ 5 V
C2
D1
C3
– 12 V
1N5818
1N4001
D2
C1
+ 12 V
1N4001
D
D
D
D
D
Figure 4.
MMBZ15VDLT1 x 10


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