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ML145506WP Datasheet(PDF) 9 Page - LANSDALE Semiconductor Inc. |
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ML145506WP Datasheet(HTML) 9 Page - LANSDALE Semiconductor Inc. |
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9 / 20 page  ML145506 LANSDALE Semiconductor, Inc. To A–Law — MSB is unchanged (sign) Invert odd numbered bits Ignore zero code suppression PDI Power Down Input The power down input disables the bias circuitry and gates off all clock inputs. This puts the VAG, Txl, RxO, RxO, and TDD outputs into a high–impedance state. The power dissi- pation is reduced to 0.1 mW when PDI is a low logic level. The circuit operates normally with PDI = VDD or with a logic high as defined by connection at VLS. TDD will not come out of high impedance for two MSI cycles after PDI goes high. ANALOG VAG Analog Ground Input/Output Pin VAG is the analog ground power supply input/output. All analog signals into and out of the device use this as their ground reference. Each version of the ML1455xx PCM codec–filter family can provide its own analog ground supply internally. The dc voltage of this internal supply is 6% posi- tive of the midway between VDD and VSS. This supply can sink more than 8 mA but has a current source limited to 400 µA. The output of this supply is internally connected to the analog ground input of the part. The node where this supply and the analog ground are connected is brought out to the VAG pin. In symmetric dual supply systems (±5, ±6, etc.), VAG may be externally tied to the system analog ground sup- ply. When RxO or RxO drive low–impedance loads tied to VAG, a pull–up resistor to VDD will be required to boost the source current capability if VAG is not tied to the supply ground. All analog signals for the part are referenced to VAG, including noise; therefore, decoupling capacitors (0.1 µF) should be used from VDD to VAG and VSS to VAG. Vref Positive Voltage Reference Input The Vref pin allows an external reference voltage to be used for the A/D and D/A conversions. If Vref is tied to VSS, the internal reference is selected. If Vref > VAG, then the external mode is selected and the voltage applied to Vref is used for generating the internal converter reference voltage. In either internal or external reference mode, the actual voltage used for conversion is multiplied by the ratio selected by the RSI pin. The RSI pin circuitry is explained under its pin descrip- tion below. Both the internal and external references are inverted within the PCM codec–filter for negative input volt- ages such that only one reference is required. External Mode — In the external reference mode (Vref >VAG), a 2.5 V reference like the MC1403 may be connected from Vref to VAG. A single external reference may be shared by tying together a number of Vref pins and VAG pins from different codec–filters. In special applications, the external reference voltage may be between 0.5 and 5 V. However, the reference voltage gain selection circuitry associated with RSI must be considered to arrive at the desired codec–filter gain. Internal Mode — In the internal reference mode (Vref =VSS), an internal 2.5 V reference supplies the reference volt- age for the RSI circuitry. RSI Reference Select Input The RSI input allows the selection of three different over- load or full–scale A/D and D/A converter reference voltages independent of the internal or external reference mode. The RSI pin is a digital input that senses three different logic states: VSS, VAG, and VDD. For RSI = VAG, the reference voltage is used directly for the converters. The internal refer- ence is 2.5 V. For RSI = VSS, the reference voltage is multi- plied by the ratio of 1.26, which results in an internal convert- er reference of 3.15 V. For RSI = VDD, the reference voltage is multiplied by 1.51, which results in an internal converter reference of 3.78 V. The device requires a minimum of 1.0 V of headroom between the internal converter reference to VDD. VSS has this same absolute valued minimum, also measured from the VAG pin. The various modes of operation are sum- marized in Table 2. RxO, RxO Receive Analog Outputs These two complimentary outputs are generated from the output of the receive filter. They are equal in magnitude and out of phase. The maximum signal output of each is equal to the maximum peak–to–peak signal described with the refer- ence. If a 3.15 V reference is used with RSI tied to VAG and a 3 dBm0 sine wave is decoded, the RxO output will be a 6.3 V peak–to–peak signal. RxO will also have an inverted signal output of 6.3 V peak–to–peak. External loads may be con- nected from RxO to RxO for a 6 dB push–pull signal gain or from either RxO or RxO to VAG. With a 3.15 V reference, each output will drive 600 Ω to 9 dBm. With RSI tied to VDD, each output will drive 900 Ω to 9 dBm. RxG Receive Output Gain Adjust The purpose of the RxG pin is to allow external gain adjust- ment for the RxO pin. If RxG is left open, then the output sig- nal at RxO will be inverted and output at RxO. Thus, the push–pull gain to a load from RxO to RxO is two times the output level at RxO. If external resistors are applied from RxO to RxG (RI) and from RxG to RxO (RG), the gain of RxO can be set differently from inverting unity. These resis- tors should be in the range of 10 k Ω. The RxO output level is unchanged by the resistors and the RxO gain is approximately equal to minus RG/RI. The actual gain is determined by tak- ing into account the internal resistors which will be in parallel to these external resistors. The internal resistors have a large tolerance, but they match each other very closely. This match- ing tends to minimize the effects of their tolerance on external gain configurations. The circuit for RxG and RxO is shown in the Block Diagram. Txl Transmit Analog Input TxI is the input to the transmit filter. It is also the output of the transmit gain amplifier. The TxI input has an internal gain www.lansdale.com Page 9 of 20 Issue A |
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