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SN74LV175APWR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV175APWR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page SN54LV175A, SN74LV175A QUADRUPLE DTYPE FLIPFLOPS WITH CLEAR SCLS400G − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS CLR CLK D Q Q L X X L H H ↑ HH L H ↑ LL H H L X Q0 Q0 logic diagram (positive logic) 1Q 9 1 C1 1D CLR CLK 1D R 1Q To Three Other Channels 4 2 3 Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. |
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