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TMPR4956C Datasheet(PDF) 6 Page - Toshiba Semiconductor

No. de pieza TMPR4956C
Descripción Electrónicos  64-Bit TX System RISC TX49 Family
Download  286 Pages
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Fabricante Electrónico  TOSHIBA [Toshiba Semiconductor]
Página de inicio  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 6 Page - Toshiba Semiconductor

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Table of Contents
ii
4.2.1
User Mode Operations ............................................................................................................4-5
4.2.2
Supervisor Mode Operations ................................................................................................... 4-7
4.2.3
Kernel Mode Operations ......................................................................................................... 4-9
4.3
Translation Lookaside Buffer ....................................................................................................... 4-15
4.3.1
Joint TLB.............................................................................................................................. 4-15
4.3.2
TLB Entry format ................................................................................................................. 4-15
4.3.3
Instruction-TLB .................................................................................................................... 4-16
4.3.4
Data-TLB.............................................................................................................................. 4-16
4.4
Virtual-to-Physical Address Translation Process ........................................................................... 4-16
5.
Cache Organization........................................................................................................................... 5-1
5.1
Memory Organization ................................................................................................................... 5-1
5.2
Cache Organization ....................................................................................................................... 5-2
5.2.1
Cache Sizes ............................................................................................................................. 5-2
5.2.2
Cache Line Lengths ................................................................................................................ 5-2
5.2.3
Organization of the Instruction Cache (I-Cache) ..................................................................... 5-2
5.2.4
Instruction Cache Address Field.............................................................................................. 5-3
5.2.5
Instruction Cache Configuration ............................................................................................. 5-3
5.2.6
Organization of the Data Cache (D-Cache) ............................................................................. 5-4
5.2.7
Data Cache Address Field ....................................................................................................... 5-4
5.2.8
Data Cache Configuration....................................................................................................... 5-4
5.3
Lock Function ............................................................................................................................... 5-5
5.3.1
Lock Bit Setting and Clearing.................................................................................................. 5-5
5.3.2
Operation during Lock ............................................................................................................ 5-6
5.3.3
Example of Data Cache Locking............................................................................................. 5-6
5.3.4
Example of Instruction Cache Locking ................................................................................... 5-6
5.4
The Primary Cache Accessing........................................................................................................ 5-7
5.5
Cache States .................................................................................................................................. 5-7
5.6
Cache Line Ownership .................................................................................................................. 5-8
5.7
Cache Multi-Hit Operation ............................................................................................................ 5-8
5.8
FIFO Replacement Algorithm ....................................................................................................... 5-8
5.9
Cache Testing ................................................................................................................................ 5-9
5.9.1
Cache Disabling ...................................................................................................................... 5-9
5.9.2
Cache Flushing ....................................................................................................................... 5-9
5.10 Cache Operations ........................................................................................................................ 5-10
5.10.1
Cache Write Policy................................................................................................................ 5-11
5.10.2
Data Cache Line Replacement .............................................................................................. 5-11
5.10.3
Instruction Cache Line Replacement ..................................................................................... 5-12
5.11 Manipulation of the Caches by an External Agent ....................................................................... 5-12
6.
Write Buffer ...................................................................................................................................... 6-1
7.
Debug Support Unit .......................................................................................................................... 7-1
7.1
Features......................................................................................................................................... 7-1
7.2
EJTAG Interface............................................................................................................................ 7-1
7.3
Debug Unit.................................................................................................................................... 7-2
7.3.1
Extended Instructions ............................................................................................................. 7-2
7.3.2
Extended Debug Registers in CP0 ........................................................................................... 7-2
7.4
Register Map ................................................................................................................................. 7-2
7.5
Processor Bus Break Function........................................................................................................ 7-2
7.6
Debug Exception ........................................................................................................................... 7-2
8.
CPU Exception ................................................................................................................................. 8-1
8.1
Introduction................................................................................................................................... 8-1
8.2
Exception Vector Locations ........................................................................................................... 8-1
8.3
Priority of Exception ..................................................................................................................... 8-2
8.4
ColdReset Exception...................................................................................................................... 8-3
8.4.1
Cause ...................................................................................................................................... 8-3
8.4.2
Processing ............................................................................................................................... 8-3
8.4.3
Servicing ................................................................................................................................. 8-3
8.5
SoftReset Exception ....................................................................................................................... 8-4
8.5.1
Cause ...................................................................................................................................... 8-4


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