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BUF01900AIDRCT Datasheet(PDF) 10 Page - Texas Instruments |
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BUF01900AIDRCT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 25 page BUF01900 BUF01901 SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006 www.ti.com 10 DATA RATES The two-wire bus operates in one of three speed modes: D Standard: allows a clock frequency of up to 100kHz; D Fast: allows a clock frequency of up to 400kHz; and D High-speed mode (or Hs mode): allows a clock frequency of up to 3.4MHz. The BUF0190x is fully compatible with all three modes. No special action is required to use the device in Standard or Fast modes, but High-speed mode must be activated. To activate High-speed mode, send a special address byte of 00001xxx, with SCL ≤ 400kHz, following the START condi- tion; xxx are bits unique to the Hs-capable master, which can be any value. This byte is called the Hs master code. (Note that this is different from normal address bytes—the low bit does not indicate read/write status.) The BUF0190x will respond to the High-speed command regardless of the value of these last three bits. The BUF0190x does not ac- knowledge this byte; the communication protocol prohibits acknowledgment of the Hs master code. On receiving a master code, the BUF0190x switches on its Hs mode fil- ters, and communicates at up to 3.4MHz. Additional high-speed transfers may be initiated without resending the Hs mode byte by generating a repeat START without a STOP. The BUF0190x switches out of Hs mode with the next STOP condition. GENERAL CALL RESET AND POWER-UP The BUF0190x responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110). The BUF0190x acknowl- edges both bytes. Upon receiving a General Call Reset, the BUF0190x performs a full internal reset, as though it had been powered off and then on. It always acknowl- edges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call data bytes other than 06h (0000 0110). The BUF0190x automatically performs a reset upon pow- er-up. As part of the reset, the BUF0190x is configured for the output to change to the programmed OTP memory val- ue, or to mid-scale, ‘1000000000’, if the OTP value has not been programmed. Table 2 provides a summary of com- mand codes. Table 2. Quick-Reference Table of Command Codes COMMAND CODE General Call Reset Address byte of 00h followed by a data byte of 06h. High-Speed Mode 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. READ/WRITE OPERATIONS: Read commands are performed by setting the read/write bit HIGH. Setting the read/write bit LOW performs a write transaction. Figure 17 and Figure 18 show the timing diagrams for read and write operations. Writing: To write to the DAC register: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF01900/BUF01901 will acknowledge this byte. 3. Send two bytes of data for the DAC register. Begin by sending the most significant byte (bits D15—D8; only bits D9 and D8 are used, and D15—D13 must not be 010 or 001), followed by the least significant byte (bits D7—D0). The register is updated after receiving the second byte. 4. Send a STOP condition on the bus. The BUF0190x acknowledges each data byte. If the mas- ter terminates communication early by sending a STOP or START condition on the bus, the DAC output will not up- date. Reading: To read the register of the DAC: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = HIGH. The BUF0190x will acknowledge this byte. 3. Receive two bytes of data. The first received byte is the most significant byte (bits D15—D8; only bits D9 and D8 have meaning, and bits D15—D12 will show the programming status of the OTP memory). See Table 3. The next byte is the least significant byte (bits D7—D0). 4. Acknowledge after receiving the first byte only. 5. Do not acknowledge the second byte of data or send a STOP condition on the bus. Communication may be terminated by the master by sending a premature STOP or START condition on the bus, or by not sending the Acknowledge. Table 3. OTP Memory Status CODE (Bits D15 − D12) OTP PROGRAMMING STATUS 0000 OTP has not been programmed. 0001 OPT has been programmed once. 0011 OTP has programmed twice. 0111 OPT has programmed three times. 1111 OTP has programmed all four times. |
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